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How can I merge several Xilinx NGC netlists to an new netlist

vhdl,xilinx,synthesis,xilinx-ise,netlist
I'm using XST (synthesis tool in the Xilinx ISE 14.7 suite) to compile VHDL source files to a netlist (*.ngc file). My code uses several Xilinx IP Cores like ChipScope ILAs for debugging, which are also pre-synthesized as ngc files. I would like to ship only one ngc file to...

how do i initialize a std_logic_vector in VHDL?

vhdl,hdl,xilinx-ise
i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test is type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0); signal ram : ram_type; ram(0) := "0010000000000100"; ram(1) := "0001000000000101"; ram(2) := "0011000000000110"; ram(3) := "0111000000000001"; ram(4) := "0000000000001100"; ram(5)...

How to prevent ISE compiler from optmizing away my array?

verilog,fpga,xilinx-ise
I'm new to Verilog, ISE, FPGAs. I'm trying to implement a simple design into an FPGA, but the entire design is being optimized away. It is basically an 2D array with some arbitrary values. Here is the code: module top( output reg out ); integer i; integer j; reg [5:0]...

VHDL simulation failed with unexpected result

vhdl,fpga,hdl,spartan,xilinx-ise
I learned VHDL 5 years back, and never used after that as I was working on different domain. Now I'm working in a project that required some work in VHDL. I have to implement SPI to program a ADF4158 device. I opened a book for syntax and tried to program....

$rtoi() is not a constant system function

verilog,xilinx-ise,icarus
I want to set size of a constant for a counter: localparam MAX_COUNT = ((debounce_per_ms * clk_freq)) + 1; parameter MAX_COUNT_UPPER = $rtoi($floor($log10(MAX_COUNT)/$log10(2))); That work well with XST (ise) and with verilator but in Icarus I've got this error : src/button_deb.v:20: error: $rtoi() is not a constant system function. I...

start point for partial reconfiguration in xilinx virtex 5 board

xilinx-ise,vivado
I,m going to learn working with partial reconfiguration xilinx boards. I've read xilinx guide and know about ISE, plan ahead and vivado. but for starting I couldn't find any example. Is there simple example codes for beginning? steps of making partial reconfiguration project is written in xilinx user guide(ug720) but...