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verilog $readmemh takes too much time for 50x50 pixel rgb image

verilog,fpga,system-verilog,quartus-ii
I am trying to compile a verilog code for FPGA programming where I will implement a VGA application. I use QuartusII and Altera. I am trying to use readmemh properly for acquiring a picture pixel by pixel. For now, I have converted a picture into rgb texts using matlab. Each...

How can I improve my ad hoc cruise control system for Nios 2?

c,embedded,nios,quartus-ii,ucos
I have written in Nios 2 an ad hoc cruise control system for a school assignment. I versioned it with github. We want the cruise control to differ at most 2 m/s for speeds >= 25 m/s. The latest improvement I could do was checking the velocities in the condition...

Use dma transfert with Cyclone V Avalon-MM for PCIe

dma,altera,pci-e,quartus-ii,qsys
Is it possible to do DMA transferts with the IP core «Cyclone V Avalon-MM for PCIe» provided by altera in Qsys (quartus 14.0) ? Altera provide an ip-core named «Cyclone V Avalon-MM DMA for PCIe» to do dma transfert. But this ip-core does not support PCIe Gen1 with 1x lane....

How to get a rgb picture into FPGA most efficiently, using verilog

image,verilog,fpga,vga,quartus-ii
I am trying to write a verilog code for FPGA programming where I will implement a VGA application. I use Quartus II and Altera DE2. At the moment, my aim is to get a 640x480 rgb image during compilation (method doesn't matter as long as it works and is efficient)....

How do I concatenate parameters and integers in verilog

verilog,altera,quartus-ii
My code for an Altera FPGA has 8 memories, that I need to initialise using memory initialization files (mifs). To enable me to instantiate memories with different mifs, I make the following changes to the memory definition file. original code module my_memory ( input clk,addr,din,wen,ren; output dout); ... ... defparam...

QuartusII 14.1.0 Debian Linux crash

linux,debian,altera,quartus-ii
I can't use Quartus 14.1.0 with Linux Debian (wheezy and Jessie) on my 64 bits computer. If I launch it on console I've got this message : [email protected]:/opt/altera/14.1/quartus/bin$ ./quartus Inconsistency detected by ld.so: dl-close.c: 743: _dl_close: Assertion `map->l_init_called' failed! And the GUI is launched correctly. But, after some minutes of...

16 bit adder using 2 bit adder as component

vhdl,quartus-ii
I am trying to create a 16-bit adder using 2-bit adders as components (which themselves use 1-bit adder as component). However, my code doesn't compile in Quartus II. Can someone help me please? Thank you very much! My project is consisted of 3 files: bit_adder.vhd, add2.vhd and add16.vhd. The error...

Error (10028): Can't resolve multiple constant drivers for net “sda” at I2C_com.vhd(185)

vhdl,fpga,quartus-ii
i'm trying to make my own I2C communication and i have a problem with multiply drivers, it's not like i don't understand them i just don't see them (i'm still fresh at vhdl), so please just take a look at my code and tell mi why is there such mistake....

Object is used but not declared?

vhdl,quartus-ii
I have the following VHDL code, its a entity of a project: library ieee; use ieee.std_logic_1164.all; library work; use work.typedef.all; entity uc is port(faaaa: in std_logic_vector(15 downto 0); phi: in std_logic; isDirect,isRam,jmp,store,NarOut,arpOut:out std_logic); end entity uc; architecture b8 of ua is signal instt : std_logic_vector(15 downto 0); signal bit7: std_logic;...