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What is the meaning of this code statement in verilog?

verilog,system-verilog,hdl
'define vend_a_drink {D,dispense,collect} = {IDLE, 2'b11} D - next_state dispense - dispense the drink collect - collect coins Given statement was included in a code written using verilog for an vending machine....

Verilog simulation x's in output

verilog,simulation,hdl,modelsim
I Have some problem verilog and cannot resolve it. Tried different changes but still no solution. The code: module Perpetual_Calender(); reg [3:0] year[277:0]; //14 different calendars can exist for 2033-1755 = 288 years reg [2:0] month[3:0][3:0]; //different calenders for combination of year and month reg [2:0] day [2:0][4:0]; //different days...

VHDL simulation failed with unexpected result

vhdl,fpga,hdl,spartan,xilinx-ise
I learned VHDL 5 years back, and never used after that as I was working on different domain. Now I'm working in a project that required some work in VHDL. I have to implement SPI to program a ADF4158 device. I opened a book for syntax and tried to program....

VHDL Signal Assignment Confusion

vhdl,hdl
I was studying VHDL and came across a question for which I could not find an answer. I understand the below example and why the result is 7: architecture SIGN of EXAMPLE is signal TRIGGER, RESULT: integer := 0; signal signal1: integer :=1; signal signal2: integer :=2; signal signal3: integer...

AXI4 (Lite) Narrow Burst vs. Unaligned Burst Clarification/Compatibility

vhdl,hdl
I'm currently writing an AXI4 master that is supposed to support AXI4 Lite (AXI4L) as well. My AXI4 master is receiving data from a 16-bit interface. This is on a Xilinx Spartan 6 FPGA and I plan on using the EDK AXI4 Interconnect IP, which has a minimum WDATA width...

VHDL: Why is output delayed so much?

vhdl,hdl,quartus
I'm learning VHDL in order to describe and demonstrate the work of a superscalar-ish pipelined CPU with hazard detection and branch prediction, etc. I'm starting small, so for practice I tried making a really simple "calculator" design, like this: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_signed.all; entity calculator is...

logic gate XOR HDL not working with Nand2Tetris

hdl
i'm not too sure why my Nand2tetris simulator keep telling me line 3 error. can anyone tell me any problem with the following code: CHIP Xor { IN a, b; OUT out; PARTS: Not(in=a, out=nota); Not(in=b, out=notb); And(a=a, b=notb, out=m); And(a=nota, b=b, out=n); Or(a=m, b=n, out=out); } ...

running a 3 to 7 Decoder using a counter

vhdl,hdl,cadence
I am trying to run my 3 to 7 decoder using the inputs coming from my counter ,all the individual codes run fine but the structural code is giving up some error This is the program for my counter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity counter is port(clk ,...

Order of size specifiers in unpacked ports

arrays,verilog,system-verilog,hdl
I was wondering what is the difference in declaring an unpacked port this way: input logic a[10]; or this way: input logic a[9:0]; I could not find the difference documented anywhere, I only know by experience that connecting two ports with these "different?" types would not cause any warning (tested...

how do i initialize a std_logic_vector in VHDL?

vhdl,hdl,xilinx-ise
i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test is type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0); signal ram : ram_type; ram(0) := "0010000000000100"; ram(1) := "0001000000000101"; ram(2) := "0011000000000110"; ram(3) := "0111000000000001"; ram(4) := "0000000000001100"; ram(5)...

Parameterized function errors

verilog,system-verilog,hdl,modelsim
I am trying to write the following systemverilog code where different parameters can be used for functions, so the same functions can be reused just by changing parameters instead of using parameterized modules. My following code compiles without error, but when I try to simulate with the testbench it gives...

Always loop Verilog

verilog,hdl
This my Verilog code to convert the number x into form x=a0*R+a1 ,e.g 51 = 5*10 +1. My code does not work, it cannot enter the always loop. `timescale 1ns / 1ps module poly( input [15:0] r, input [15:0] x, output reg[15:0] a1, output reg [15:0] a0, output finish, input...

Verilog Vending machine FSM

verilog,fpga,hdl
I am trying to build a finite state machine in verilog for a vending machine that accepts 5,10, 25 cents as inputs and then output a a soda or diet and also output the appropriate change(as the number of nickels). I am currently getting an error that says ERROR:HDLCompiler:806 -...

Expression out of bounds on MATLAB with HDL coder app

arrays,matlab,loops,vhdl,hdl
I try to get the VHDL code corresponding to my simulation on MATLAB with HDL coder app, but I get a first error at the line 25 when I build the MATLAB code on the HDL coder app: Index expression out of bounds. Attempted to access element 15. The valid...

Verilog Testbench constant exp and pram compilation and simulation errors

verilog,simulation,hdl,modelsim
Source Code: module SingleOneBit(N,T); parameter integer w; //width or number of inputs N input wire [w-1:0] N; output wire T; wire[w*(w-1):0] N1; //for anding all possible combinations of 2 bits wire R; // for oring all tha ands. If R = 1 then N contians more than one bit with...