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Error (10028): Can't resolve multiple constant drivers for net “sda” at I2C_com.vhd(185)

vhdl,fpga,quartus-ii
i'm trying to make my own I2C communication and i have a problem with multiply drivers, it's not like i don't understand them i just don't see them (i'm still fresh at vhdl), so please just take a look at my code and tell mi why is there such mistake....

My verilog VGA driver causes the screen to flicker (Basys2)

verilog,fpga,system-verilog,xilinx,vga
I'm trying to recreate Adventure(1979) in Verilog and so far I have character movement, collision and map generation done. It didn't flicker that much before I separated the maps into modules now it flickers constantly. When I was looking up this issue, I found out that the clock on the...

verilog $readmemh takes too much time for 50x50 pixel rgb image

verilog,fpga,system-verilog,quartus-ii
I am trying to compile a verilog code for FPGA programming where I will implement a VGA application. I use QuartusII and Altera. I am trying to use readmemh properly for acquiring a picture pixel by pixel. For now, I have converted a picture into rgb texts using matlab. Each...

How to assign pins to natural type of ports in Xilinx

vhdl,fpga,xilinx
How can I assign natural types of ports to pins in XILINX UCF file? Generic ( nr_ro : natural := 32 ); Port ( clk_i : in STD_LOGIC; rst_i : in STD_LOGIC; sel1_i : in natural range 0 to nr_ro-1; sel2_i : in natural range 0 to nr_ro-1; bit_o :...

Verilog asynch mem in Xilinx

verilog,fpga,xilinx,synthesis
I am trying to create a memory shift operation in verilog and was wondering the best way to do it. An example code is: reg [MSB:0] a [0:NO_OF_LOCATIONS]; // after some processing for(i =0; i <= NO_OF_LOCATIONS; i= i+1) a[i] = a[i+1] If I use a ROM in Xilinx it...

Code for 8 point DCT using shifters and adders

verilog,fpga,system-verilog
I've written code for an 8 point dct using shifters and adders. I didn't get any errors but while simulating I didn't get the expected result. Logically it is correct, as I have mathematically solved it. Please help me to resolve this flaw. Expected pattern is X(0)=5 y(0)=1792 X(1)=4 y(1)=710...

Verilog pipeline

verilog,fpga
I'm trying to make a easy game using HD44780 LCD. My idea is to use a BUSY signal to hold off any commands until previous command is executed. I want to use counter and case for sequences of commands while another block is holded by BUSY signal. Something like this:...

Some Course/book about FPGA? [closed]

fpga
I'm starting my journey with FPGAs and I bought a low cost with this specifications : FPGA: EP2C8Q208C8N SDRAM: 256 M bit/ 36 M Byte CFI_FLASH: 64 M bit/ou 8 M Byte SRAM: 256 K x 16/ 4 M bit EPCS: EPCS16/ M25P32 (Configure FPGA) CLK_INPUT: 50 MHz Does anyone...

FPGA verilog code upload speed and size limit

fpga,computer-architecture,cpu-architecture
I have two question about FPGA 1. I would like to know how large FPGA chip size would be if I create a full CPU with pipeline. Any calculation method or paper that describes how I can calculate the chip size? 2. If I upload fairly reasonable functions (or modules)...

Module without an EN - VHDL

vhdl,fpga
I've a module that when I don't use it, it must go to reset state so I don't need a moduleEN. So, a module like this: process(clock, reset) begin if reset = '0' then elsif rising_edge(clock) then end if; It's correct for a synthesizer? Or it's better: process(clock, reset) begin...

I cannot get the Xilinx uartlite IP to work

vhdl,verilog,fpga,xilinx,vivado
Im attempting to use the Xilinx uartlite 2.0 IP with an AXI4-lite interface to transmit a byte without a microblaze processor. Unfortunately, all the ready signals remain low after I set the data and valid signals and the tx signal never transmits. I've included my simulation results. any ideas? ...

What is the difference between these verilog codes?

verilog,fpga
I'm was following a tutorial to blink a led in my fpga. These are the codes presented : 1) module LED ( input [17:0] SW, output reg [17:0] LEDR ); assign led = switch; endmodule 2) -------- module LED ( input [17:0] SW, output reg [17:0] LEDR ); always @(*)...

FIFO error: can't find control signal - VHDL

vhdl,fpga,fifo
I've found a VHDL FIFO code and tryed to modify it to use with two different clocks, one for write and one for read. I've tryed the code and seems to work in simulation, but when I try to synthesize it I get this error: "Can't find control signal for...

FPGA: Divide range by fixed number using a look-up table

math,signal-processing,vhdl,fpga,lookup-tables
I have implemented a block in an FPGA which supports hardware multiplication. This block does some division by using hardly any logic elements because it's able to use some internal DSP. This block has to be ported to another design, but here I have 2k less logic elements and no...

Verilog Vending machine FSM

verilog,fpga,hdl
I am trying to build a finite state machine in verilog for a vending machine that accepts 5,10, 25 cents as inputs and then output a a soda or diet and also output the appropriate change(as the number of nickels). I am currently getting an error that says ERROR:HDLCompiler:806 -...

Multiplication by power series summation with negative terms

vhdl,verilog,fpga,vlsi
How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again. For example 0.3545 = 2^-2 + 2^-4 + ... I have...

verilog code to convert binary input into residue number system

verilog,fpga,system-verilog
I have written a code which converts our number which is in binary into residue using a look up table. First, I have made a memory having both read and write enables and stored values. During 'we' , 'a' is my input which is of 8 bit... for every bit...

Why we use CORDIC gain?

math,fpga,cordic
I'm studying the cordic. And I found the cordic gain. K=0.607XXX. From CORDIC, K_i = cos(tan^-1(2^i)). As I know the K is approched 0.607xxx.when I is going to infinity this value come up with from all K multiplying. I understand the reason of exist each k. But I am curioused...

If statement using vhdl

if-statement,vhdl,fpga,xilinx
I am designing counter using vhdl using planahead software, anyway I am using if statment but it gave many errors . the purpose of the counter is to count Ascending/Descending from 1 to 10 and the opposite. In case of Ascending I reset the out when it get to 9...

Can signals be used instead of hard coding values multiple times?

vhdl,fpga,modelsim,quartus
I'm a student learning VHDL and have a pretty basic question. I've read that signal assignments don't take place immediately. So the following would not work as expected: x <= y; z <= not x; So I understand that assignments are not immediate / don't happen sequentially, but I have...

How to prevent ISE compiler from optmizing away my array?

verilog,fpga,xilinx-ise
I'm new to Verilog, ISE, FPGAs. I'm trying to implement a simple design into an FPGA, but the entire design is being optimized away. It is basically an 2D array with some arbitrary values. Here is the code: module top( output reg out ); integer i; integer j; reg [5:0]...

Why this verilog assignment is wrong?

verilog,fpga
I'm trying to solve this problem from altera Lab. Here's my code : module AlteraLAB2 ( input [17:0] SW, output [17:0] LEDR, output [7:0] LEDG ); wire S; wire [7:0] X,Y,M; //Use switch SW17 on the DE2 board as the s input, switches SW7−0 as the X input and SW15−8...

using when…else statment in port map

vhdl,fpga
i can't find anything about using when...else statment in port map. It seems to be a correct form but when i compile i see a error like this : Error (10500): VHDL syntax error at Device.vhd(68) near text "when"; expecting ")", or "," It's probably a silly mistake cause i'm...

Synthesizing a counter with an asynchronous edge-triggered reset

verilog,fpga
I want to synthesize a clock counter with an asynchronous edge-triggered reset: the counter increments on every clk rising edge, and resets to 0 on the rising edge of a rst signal. The counter reset to 0 must be edge-triggered since the rst signal may stay high indefinitely. Here's what...

What is the Intel Strata Flash Memory on Spartan-3E Starter Kit?

flash,intel,fpga,spartan
What would an use case scenario be like? I know that there's plenty information about this in the user manual, but i'm a beginner and don't know really how to handle that information. Thank you for your time.

VHDL integer range inclusive? Difference in FPGA vs. simulation

vhdl,fpga,modelsim,altera
I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand. I have a 50MHz clock source. I have a signal defined as: SIGNAL ledCounter : integer range 0 to 25000000 := 0; When the ledCounter reaches 25,000,000 I toggle an LED...

VHDL simulation failed with unexpected result

vhdl,fpga,hdl,spartan,xilinx-ise
I learned VHDL 5 years back, and never used after that as I was working on different domain. Now I'm working in a project that required some work in VHDL. I have to implement SPI to program a ADF4158 device. I opened a book for syntax and tried to program....

Arrays as buffer VHDL

vhdl,fpga
I need to create a FIFO buffer in VHDL. I need to use a 2 dimensional array to storage data like (number of data)(n-bit data). If I create a single "big" array that storage for example 1000 entrys. Every new data clock I storage one slot. And every output data...

What is wrong in this verilog code?

verilog,fpga
I'm studying verilog and trying to apply the concepts in my fpga. It supossed to work in this way : When Switch 1 is on, all red leds turn on. When Switch 2 is on, all green leds turn on. When Switch 3 is on, all leds turn on. The...

If statement using vhdl-counter

if-statement,vhdl,fpga
It'z DFF counter counts from 0 to 10, and from 10 to 0. There z switch to switch between Ascending/Descending. On of the guys in this website helped me to solve the if statement problem but it looks itz not allowed to use it outside the process , si if...

SPI interface works in simulation but not on actual hardware

vhdl,fpga,xilinx
I am trying to send multiple bytes on the SPI bus during the transmit window. Initially I am acquiring data from the flash ADC when the input pulse is high, then calculating its average and transmitting each average value sequentially on the SPI bus. I got the SPI vhdl module...

Why use multiple clocks of the same speed in an FPGA design?

vhdl,clock,fpga
I very recently began experimenting with FPGAs. In researching things around the net I've noticed in several places that designs might use multiple separate PLL clocks of the exact same speed. Why is that? One example I will give is this site: Parallella Linux Quick Start They have their FCLK_CLK1...

Inbuilt Adders used in FPGA

verilog,fpga,system-verilog
when we write code for adder C=A+B then which adders are used by IST for implementation in FPGA . Can we built adders faster than that so that our delay get reduces by compromising the Area.

Signal current cannot be synthesized, bad synchronous description

vhdl,fpga
I have a error while Synthesize this code in Xillinx. This error is: Analyzing Entity in library (Architecture ). ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description. entity Parking is port( A, B ,reset: in std_logic; Capacity : out std_logic_vector(7 downto 0)); end Parking; architecture...

How do I read the status register of a Virtex 5 in a JTAG chain?

fpga,jtag,virtex
I'm working on an XUPV5-LX110T and I'm trying to read the status register over JTAG. I'm getting incorrect data, but I can't see why. I seem to be getting all zeros. I suspect it has to do with the order of the JTAG chain, but I'm not sure how I...

How to get a rgb picture into FPGA most efficiently, using verilog

image,verilog,fpga,vga,quartus-ii
I am trying to write a verilog code for FPGA programming where I will implement a VGA application. I use Quartus II and Altera DE2. At the moment, my aim is to get a 640x480 rgb image during compilation (method doesn't matter as long as it works and is efficient)....

2's compliment input and using vhdl library for signed input

vhdl,fpga,xilinx
My input data is 2's compliment and I designed the input is signed number and the all of operation is used signed number,the library i used ieee.numeric_std.all, but when i do ‘+’ an error occurred "found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"". So...

How to get rid of scale factor from CORDIC

math,vhdl,fpga,rtl,cordic
From CORDIC, K_i = cos(tan^-1(2^i)). As I know the K is approached 0.607xxx. How do I approach to 0.607xxx? Also does it mean that I can use 0.607xxx instead of cos(tan^-1(2^I))? I am citing from this article. I am trying to implement hyperbolic tanh function. And so far I understand...

how I know the fpga_0_RS232_RX_pin of Atlys spartan-6

fpga,xilinx-edk
I want to configure RS232 of an ATLYS SPARTAN 6 XC6SLX45 I want to configure the pin fpga_0_RS232_RX_pin on the board but I don't know how to configure the suitable pin for it.How can I do that? system.ucf: # Generic Template Net fpga_0_RS232_RX_pin LOC=; Net fpga_0_RS232_TX_pin LOC=; Net fpga_0_clk_1_sys_clk_pin LOC...

hardware implementation of Modulo m adder

verilog,fpga,system-verilog,computer-architecture
I have 8 inputs whose modulo sum i have to take with modulus m.i know algorithm for 2 input but it is not working here. eg i have sum=sum0+sum1+sum2+sum3+sum4+sum5+sum6+sum7 and i have to take mod m of sum.How to do this rom hardware implementation point of view? i aslo write...

Process evaluated too many times

vhdl,fpga
I have a simple design where I read incoming bytes from an RS-232 port and later "parse" them. I tried to divide this into 2 processes: first one receives bits from the serial port and tries to frame them - if it succeeds, it assigns the result to a signal...

How long takes a multiplier function on FPGA? and is it possible to calculate this time?

fpga
I have implemented a hardware architecture on FPGA and i use some multiplier function on this architecture , I'd like to know is there any way or method on ISE software or hardware (by using chip scope) to calculate the maximum delay time of each section/step? for example i want...

Can I access delayed value in SystemVerilog assertion

fpga,verification,system-verilog,assertion
I want to use an old value of a signal in a SystemVerilog assertion. This is what I am currently doing logic [ADDRESS_WIDTH-1:0] old_address [1:0]; [email protected](posedge rdclock) begin old_address[0] <= rdaddress; old_address[1] <= old_address[0]; end property FooBar; @(posedge rdclock) rden |-> ##2 q == mem[old_address[1]]; endproperty Baz: assert property (FooBar);...

verilog code containing adders

verilog,fpga,system-verilog
i write the verilog code which contain only adders. In this g,h are 10 bits and r5(main output) is of 11 bits. When i take r5 as 11 bits then i am not getting correct output but when i take r5 as 10 bits then i am getting correct. but...