FAQ Database Discussion Community


How to give more memory to Apache

php,algorithm,apache,cpu
I am using PHP with Apache 2.4 on Centos 7 to run a very CPU intensive probabilistic model. It took 8 days to run it on my home computer so I decided to move it in to a Cloud service. So I configured it and now it takes only 5...

multiple cores being used one a thread (>25% CPU usage on quadcore)

java,multithreading,cpu,taskmanager
I've just started programming in Java, and I'm interested in how computers distribute their CPU load. I have made a very basic program that creates a window and makes a box and line move. While testing this, I looked at Task Manager; Task manager said I was using ~1% of...

Are cycles in computing equal to time?

performance,time,cpu,hardware,cycle
I have a book describing energy saving compiler algorithms with a variable having "cycles" as measuring unit for the "distance" until something happens (an HDD is put into idle mode). But the results for efficiency of the algorithm have just "time" on one axis of a diagram, not "cycles". So...

Why am I maxing out on resources and CPU usage? [closed]

wordpress,cpu
Just recently my site has been maxing the resource and CPU usage. All I've done were a few minor styling changes and I'm wondering what is using so many resources. Is it possible that a lot of activity in the backend of WordPress would cause hosting (GoDaddy) to shut the...

Why the CPU compiles the GPU shader?

caching,compilation,shader,gpu,cpu
To understand in general how GPU's cache support work, I read some information and understood this: CPU compiles shader and transmit resulting code of shader to GPU to execute and also save it to the disk. If necessary to execute the same shader, GPU get it saved binary code directly...

CPU new features enabled in Linux kernel

linux-kernel,cpu
If the CPU has some new features, how does the Linux kernel handle this ? From what I remembered, PAE does not need to rebuild the entire the system and Linux seems like just installing the driver and things work. Say, if the CPU provides more execution modes, Do we...

Why MESI protocol may result in write action that is followed by write action to the same address?

caching,architecture,cpu,l1-cache
MESI protocol used with write-back. 2 cores on a single processor, only L1 caches for simplicity. address A was never used core 1 initiated write action to address A. It results in data saved to its cache and state is set to M. core 2 initiated write action to address...

How many interrupts does my cpu have per second?

linux,cpu,interrupt
I have a 2.6 GHz Intel Core i7 running Linux. I am wondering how many interrupts on average my CPU gets per second. Does anyone have a suggestion?...

1MiB = 1024KiB = 2^10. Nonetheless, why not use just 1000 byte instead 1024 to calculate size? [closed]

memory,binary,size,cpu
1024 = 2 to the power 10. Computers use binary system where the base is 2 (0 and 1). Humans use decimal system where the base is 10. So if I have 1 byte which contains 8 bit in modern computers I can represent up to 256 different states, possibilities,...

each of 3 ALU+decoders walk on 3 different conditional branches on `switch`/`case` simultaneously?

x86,cpu,x86-64,intel,hyperthreading
As known, on Intel x86_64 the Hyper Threading allow to use shared execution units (ALUs, ...) from different threads simultaneously - this is known as Simultaneous multithreading (SMT). And known, that threads, which executed on Hyper Threading virtual cores, can process different sequences of instructions - code of different processes,...

How can a branch instruction be mispredicted AND retired?

performance,optimization,x86,cpu,cpu-architecture
Intel has a hardware event counter called: BR_MISP_RETIRED.ALL_BRANCHES where the description says: Mispredicted macro branch instructions retired. But retired instructions are those which were correctly-required: Modern processors execute much more instructions that the program flow needs. This is called "speculative execution". Then the instructions that were "proven" as indeed needed...

How to reduce OpenGL CPU usage and/or how to use OpenGL properly

c++,opengl,graphics,cpu
I'm working a on a Micromouse simulation application built with OpenGL, and I have a hunch that I'm not doing things properly. In particular, I'm suspicious about the way I am getting my (mostly static) graphics to refresh at a close-to-constant framerate (60 FPS). My approach is as follows: 1)...

How many 32-bit integer ops can a Haswell core perform at once?

x86,cpu,simd,avx,cpu-speed
In the context of preparing some presentation, it occurred to me that I don't know what the theoretical limit is for the number of integer operations a Haswell core can perform at once. I used to naively assume "Intel cores have HT, but that's probably parallelizing different kinds of work,...

Undefined CPU instructions without execution cause bugs?

cpu,speculative-execution
Now I try to dispatch codes dynamically, for example, SSE, AVX and so on. In a binary file, all codes which will be dispatched at the time of execution are bundled. I worry that undefined CPU instructions in a code path which will not be executed in the CPU cause...

Which one is right one in pipelining?

cpu,pipeline,gantt-chart
I'm studying CPU pipelining, and had a trouble. I want to know which one is right pipelining in below picture In my opinion, the first Gantt chart is kinda "structural hazard" becuase "IF" stage is partially overlapped. I think that using one stage for two instruction is not allowed. So...

Can x86_64 CPU execute two same operations on the same stage of pipeline?

x86,cpu,x86-64,intel,cpu-architecture
As known Intel x86_64 processors are not only pipelined architecture, but also superscalar. This is mean that CPU can: Pipeline - At one clock, execute some stages of one operation. For example, two ADDs in parallel with shifting of stages: ADD(stage1) -> ADD(stage2) -> nothing nothing -> ADD(stage1) -> ADD(stage2)...

Linux echo cpu (core) name/number for a given shell in PBS

linux,cpu,cpu-usage,tbb,pbs
I have a simple C++ code that uses Intel's TBB to run a list of scripts on a cluster using PBS. I want to confirm that I am using all the cores as intended. Each node has 16 cores. I have created the scripts to take varying amounts of time...

Which are the operands in Lc3 instruction?

assembly,cpu,cpu-registers,computer-architecture,lc3
I read on Wiki Opcodes that the operand of an Lc3 instruction is the data that the instruction acts on. For this Lc3 instruction (from Lc3 Instructions) Would the operands be both destination register and PCoffset9 or just destination register based off that definition?...

When writing a CPU emulator, how do you choose between simulating a 16, 32, or 64 bit processor?

emulator,cpu
If I were to write a really simple CPU Emulator, how would you determine how many bits it is, i.e 16 bits or 32 bits?

Incorrect act OpenCl/C++ script on CPU and GPU

c++,opencl,gpu,cpu
I have transfered OpenCl/C++ script to new machine (Intel(R) Core(TM) i5-4570 CPU @ 3.20GHz, NVIDIA TESLA C2070). I ran it successfully on GPU and I got correct results (Here when I tried run it on CPU it gave me incorrect results 0), then I wanted to run it on CPU...

How many words can be in the address space?

64bit,cpu,memory-address,computer-architecture,processor
Here is the problem I am working on The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address space of the workstation? I defined the different terms in the problem...

How to open and read “/proc/cpuinfo” on Android device in Delphi

android,delphi,cpu,firemonkey
Could anyone advise me how to open and read "/proc/cpuinfo" on Android device in Delphi? Original code: var i: integer; FS: TFileStream; LBuffer: TBytes; begin if FileExists('/proc/cpuinfo') then begin FS:= TFileStream.Create('/proc/cpuinfo', fmOpenRead); try SetLength(LBuffer, FS.Size); FS.ReadBuffer(Pointer(LBuffer)^, Length(LBuffer)); for i:= 0 to Length(LBuffer) - 1 do Memo1.Lines.Add(LBuffer[i]); finally FS.Free; end; end;...

How to get CPU utilization in % in terminal (mac)

osx,terminal,cpu
Ive seen the same question asked on linux and windows but not mac (terminal). Can anyone tell me how to get the current processor utilization in %, so an example output would be 40%. Thanks

How to maximize the use of the number 0 to optimize a program [closed]

c++,optimization,cpu,hardware
I was listening to a lecture at a C++ convention and speaker said to prefer zero above all other constants: "Zero is special because a bunch of operations within the machine language of any CPU architecture have zero built in them." (https://www.youtube.com/watch?v=ea5DiCg8HOY) Can someone here give me a concrete example...

How many bits are in the address field for a directly mapped cache?

caching,system,cpu,computer-architecture,cpu-cache
This is a question based on Direct Mapped Cache so I am assuming that it's ok to ask here as well. Here is the problem I am working on: The Problem: " A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte...

Websites use server or client hardware resources?

resources,cpu,hardware,cpu-usage,ram
When a user visits a website which runs an intensive script, does the web server handle it by using its own CPU and RAM, or does it use the users' resources?

My Java program reaches 80% cpu usage after 20-30 min

java,database,web-crawler,cpu
I have a java program that crawls for some data on some sites and inserts it into the database. The Program keeps doing this : Get the html Extract the relevant data with some splits Insert into to database For the first 5-10 min it runs perfectly and very fast...

Index register in cpu (Computer org. and arc.)

indexing,cpu,cpu-registers,computer-architecture,cpu-architecture
Can index register have negative value? For example: at start Xr is 0, and then we need to decrement it? What will be the value of Xr?

High CPU Usage OpenGL Ver 3.1 + SDL2

c++,opengl,sdl,cpu
In my project I use SDL2 + OpenGL Ver 3.1. There is simple code. Function VPreRender() is called when I want to clear buffer and start to draw in it. After that, when I want to show this buffer on the screen, I use functions VPostRender(). These functions are called...

Avoiding CPU Contention

c++,cpu,average,chrono
I have a program that I want to calculate its time of execution : #include <iostream> #include <boost/chrono.hpp> using namespace std; int main(int argc, char* const argv[]) { boost::chrono::system_clock::time_point start = boost::chrono::system_clock::now(); // Intructions to burn time boost::chrono::duration<double> sec = boost::chrono::system_clock::now() - start; cout <<"---- time execution is " <<...

Substraction in assembly 8086 sets wrong flags

assembly,binary,cpu,cpu-registers,8086
I am trying to do a simple math calculation. Here is my code: mov al, 128 sub al, -128 I need to know which flags are set by the sub instruction. My calculations are like this. Starting with the idea that sub is the same as +(- your number). Starting...

Monitor CPU spikes of any process over X percent for Y seconds

.net,vb.net,performance,cpu,performancecounter
I would like to run a .NET console application on our Windows Server 2008 box, which monitors CPU usage every 2 seconds. If any single application uses > 30% CPU, two times in a row, it should be logged. I will execute "CheckCpu" every 2 seconds... but my problem is,...

Set cpu affinity on a loadable linux kernel module

c,module,kernel,cpu,affinity
I need to create a kernel module that enables ARM PMU counters on every core in the computer. I have trouble setting the cpu affinity. Ive tried sched_get_affinity, but apparently, it only works for user space processes. My code is below. Any ideas? #define _GNU_SOURCE #include <linux/module.h> /* Needed by...

Why isn't the distinction between CPUs more ubiquitous?

cpu,executable,machine-code
I know that every program one writes has to eventually boil down to machine code - that's what compilers produce, that's what executable files consist of, and that's the only language that processors understand. I also know that different processors may have different instruction sets (I know 65c816 assembly, and...

How to fully take advantage of multi-cores by python

python,multithreading,cpu,cpu-usage
I used python to execute this program on Ubuntu import thread import time # Define a function for the thread def print_time( threadName, delay): count = 0 while True: count += 1 # Create two threads as follows try: for index in xrange(1,50000): thread.start_new_thread( print_time, ("Thread-" + str(index), 0, )...

How to call a CPU instruction from C#?

c#,optimization,cpu,hammingweight
My processor (Intel i7) supports the POPCNT instruction and I would like to call it from my C# application. Is this possible? I believe I read somewhere that it isn't, but the JIT will invoke it if it finds it available but what function would I have to call that...

If we use memory fences to enforce consistency, how does “thread-thrashing” ever occur?

c++,multithreading,concurrency,x86,cpu
Before I knew of the CPU's store buffer I thought thread-thrashing simply occured when two threads wanted to write to the same cacheline. One would prevent the other from writing. However, this seems pretty synchronous. I later learnt that there is a store buffer, which temporarily flushes the writes. It...

Round Robin Algorithm, processes dont finish executing

java,algorithm,cpu,scheduler,round-robin
I'm writing a simple cpu scheduler simulator, currently im at Round Robin algorithm. At this little piece of code, my way of implementing it is this: take the total sum of the burst time from user input for keeping track when this block should finish. as long as the sum...

Are correct branch predictions free?

cpu,cpu-architecture
Let's say you make some code that has an if statement and condition in that if statement always ends up being true for the entire run of your program, but that it can't be known at compile time that the condition is always true (maybe its specified on the command...

How can I know that my CPU shares the vector registers among the cores or each core has its private ones

cpu,cpu-registers,cpu-architecture
How can I know that my CPU shares the vector registers among the cores or each core has its private ones? Where can I get the references? I hope to use multi-threading and SIMD to optimise my program's floating-point computation. Will they cause any conflicts?...

IO and CPU Bound calls with Async APIController in a Four layers application

iis,asp.net-web-api,io,cpu,scalability
I have a four layer application: HTML UI layer making AJAX calls to a UI Service (Web APIController). UI Service which is a Web API controller. UI Service calls App Service. App Service layer which has methods that call database directly through EF as well as make calls to other...

Hardware shuts down on start up [closed]

cpu,hardware,desktop,overheating
What would you do if this happened to you? I have a desktop system. I took it apart (kept the tower in tact) and drove for 8 hours to visit my cousin. I set up the computer again and powered it on. This time, it starts up and then dies....