vhdl,quartus-ii , 16 bit adder using 2 bit adder as component


16 bit adder using 2 bit adder as component

Question:

Tag: vhdl,quartus-ii

I am trying to create a 16-bit adder using 2-bit adders as components (which themselves use 1-bit adder as component). However, my code doesn't compile in Quartus II. Can someone help me please? Thank you very much!

My project is consisted of 3 files: bit_adder.vhd, add2.vhd and add16.vhd. The error happens in add16.vhd:

--- bit_adder.vhd
-- description of 1 bit adder
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BIT_ADDER is
        port( a, b, cin         : in  STD_LOGIC;
              sum, cout         : out STD_LOGIC );
end BIT_ADDER;

architecture BHV of BIT_ADDER is
begin

        sum <=  (not a and not b and cin) or
                        (not a and b and not cin) or
                        (a and not b and not cin) or
                        (a and b and cin);

        cout <= (not a and b and cin) or
                        (a and not b and cin) or
                        (a and b and not cin) or
                        (a and b and cin);
end BHV;

-- below is add2.vhd, a 2-bit Adder. adds two 2-bit numbers together using two 1-bit adders

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity add2 is
    port( a, b      : in    STD_LOGIC_VECTOR(1 downto 0);
          ans       : out   STD_LOGIC_VECTOR(1 downto 0);
          cout      : out   STD_LOGIC       );
end add2;

architecture STRUCTURE of add2 is

-- Component: two 1-bit adders

component BIT_ADDER
    port( a, b, cin     : in  STD_LOGIC;
          sum, cout     : out STD_LOGIC );
end component;

signal c0, c1 : STD_LOGIC;
begin

c0 <= '0';
b_adder0: BIT_ADDER port map (a(0), b(0), c0, ans(0), c1);
b_adder1: BIT_ADDER port map (a(1), b(1), c1, ans(1), cout);

END STRUCTURE;

-- add16.vhd -- set as top level entity

LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity add16 is
    port (a, b : in std_logic_vector(15 downto 0);
            sum1 : out std_logic_vector(15 downto 0);
            cout : out std_logic_VECTOR(1 downto 0)); --_vector);
end add16;

architecture arch16 of add16 is
    component BIT_ADDER 
        port( a, b, cin         : in  STD_LOGIC;
              sum, cout         : out STD_LOGIC );
    end component;

    component add2
        port (a, b      : in    STD_LOGIC_VECTOR(1 downto 0);
          ans       : out   STD_LOGIC_VECTOR(1 downto 0);
          cout      : out   STD_LOGIC       );
    end component;

    signal c0, c1, c2, c3, c4, c5, c6, c7  : std_LOGIC_VECTOR(1 downto 0);
    begin
    c0 <='00'; --Error (10500): VHDL syntax error at add16.vhd(26) near text "'";  expecting "(", or an identifier, or  unary operator

    D_adder0: add2 port map (a(0), b(0), c0, sum1(0), c1);
    D_adder1: add2 port map (a(1), b(1), c0, sum1(1), c2);
    D_adder2: add2 port map (a(2), b(2), c0, sum1(2), c3);
    D_adder3: add2 port map (a(3), b(3), c0, sum1(3), c4);
    D_adder4: add2 port map (a(4), b(4), c0, sum1(4), c5);
    D_adder5: add2 port map (a(5), b(5), c0, sum1(5), c6);
    D_adder6: add2 port map (a(6), b(6), c0, sum1(6), c7);
    D_adder7: add2 port map (a(7), b(7), c0, sum1(7), cout);
    end arch16;

Answer:

1) The modules add2 and add16 must have a cin port, Why don't you add it to your design? If you want to get the correct result all the modules must have "carry in". The technique you used is Carry Ripple Adder, then in add16 each block (instance) must have a cin port that is provided from the previous block.

2) In the module add16 why the signals c1, c2, ... are 2 bits? Each block needs a cin port that is 1 bit. Also you don't need the signalc0, because in the module add16, c0 is the same cin.

3) In the module add16 why the ports of each instance (a,b,sum1) is 1 bit. It must be 2 bits.

4) In the module add16 you don't need the component BIT_ADDER. You can remove it.

I edited your code with the above changes. I simulated it and could get the correct result in Modelsim. (I didn't change the module BIT_ADDER) :

------------------------------- add2 ---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;


ENTITY add2 IS
    PORT( a, b  : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
          cin   : IN  STD_LOGIC;
          ans   : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
          cout  : OUT STD_LOGIC
    );
END add2;

ARCHITECTURE STRUCTURE OF add2 IS

    COMPONENT BIT_ADDER
        PORT( a, b, cin  : IN  STD_LOGIC;
                sum, cout  : OUT STD_LOGIC
        );
    END COMPONENT;

    SIGNAL c1 : STD_LOGIC;

BEGIN

    b_adder0: BIT_ADDER PORT MAP (a(0), b(0), cin, ans(0), c1);
    b_adder1: BIT_ADDER PORT MAP (a(1), b(1), c1, ans(1), cout);

END STRUCTURE;



------------------------------- add16 ---------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY add16 is
    PORT (  a, b : IN  std_logic_vector(15 DOWNTO 0);
            cin  : IN  STD_LOGIC;
            sum1 : OUT std_logic_vector(15 DOWNTO 0);
            cout : OUT std_logic);
END add16;

ARCHITECTURE arch16 OF add16 IS

    COMPONENT add2
        PORT(  a, b      : IN    STD_LOGIC_VECTOR(1 DOWNTO 0);
               cin       : IN    STD_LOGIC;
               ans       : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
               cout      : OUT   STD_LOGIC);
    END COMPONENT;

    SIGNAL c1, c2, c3, c4, c5, c6, c7  : std_LOGIC;

BEGIN

    D_adder0: add2 PORT MAP ( a(1  DOWNTO 0)  , b(1 DOWNTO 0)  , cin, sum1(1 DOWNTO 0)   , c1  );
    D_adder1: add2 PORT MAP ( a(3  DOWNTO 2)  , b(3 DOWNTO 2)  , c1 , sum1(3 DOWNTO 2)   , c2  );
    D_adder2: add2 PORT MAP ( a(5  DOWNTO 4)  , b(5 DOWNTO 4)  , c2 , sum1(5 DOWNTO 4)   , c3  );
    D_adder3: add2 PORT MAP ( a(7  DOWNTO 6)  , b(7 DOWNTO 6)  , c3 , sum1(7 DOWNTO 6)   , c4  );
    D_adder4: add2 PORT MAP ( a(9  DOWNTO 8)  , b(9 DOWNTO 8)  , c4 , sum1(9 DOWNTO 8)   , c5  );
    D_adder5: add2 PORT MAP ( a(11 DOWNTO 10) , b(11 DOWNTO 10), c5 , sum1(11 DOWNTO 10) , c6  );
    D_adder6: add2 PORT MAP ( a(13 DOWNTO 12) , b(13 DOWNTO 12), c6 , sum1(13 DOWNTO 12) , c7  );
    D_adder7: add2 PORT MAP ( a(15 DOWNTO 14) , b(15 DOWNTO 14), c7 , sum1(15 DOWNTO 14) , cout);

END arch16;

Related:


generic adder “inference architecture”: simulation error


vhdl,xilinx,modelsim,inference
So, I have to create a generic N-bit adder with carry in and carry out. I have made two fully working architectures so far, one using the generate function and one using the rtl description as follows: entity: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder_n is generic (N: integer:=8);...

Multiple behaviours for single entity


testing,process,entity,vhdl
I wrote a VHDL Testbench which contains the following : Lots of signal declarations UUT instantiations / port maps A huge amount of one-line concurrent assignments Various small processes One main (big) process which actually stimulates the UUT. Everything is fine except the fact that I want to have two...

Accessing a signal in both structural and behavioural architecture


architecture,signals,vhdl,counter
I have defined the structural architecture of a module e.g. architecture structural of my_entity is signal counter : integer := 0; begin MODULE port map(......count => counter.....); --this is an inout port end structural; I would like to implement a counter which is incremented based on a change in an...

Writing a Module Which Prevent Overwriting Previous Data in RAM


vhdl,ram
The Problem I have a channel which contains a 512 deep piece of RAM. I have a control block which tells this channel when to write and when to read. When it writes, the write pointer will increase linearly over each clock cycle so long as the capture flag is...

How can I merge several Xilinx NGC netlists to an new netlist


vhdl,xilinx,synthesis,xilinx-ise,netlist
I'm using XST (synthesis tool in the Xilinx ISE 14.7 suite) to compile VHDL source files to a netlist (*.ngc file). My code uses several Xilinx IP Cores like ChipScope ILAs for debugging, which are also pre-synthesized as ngc files. I would like to ship only one ngc file to...

VHDL simulation stuck in for loop


loops,vhdl,multiplication
I'm doing simulation testing for some VHDL I wrote and when I run it in ModelSim it gets stuck. When I hit 'break' it has an arrow pointing to the For loop in the following function: function MOD_3 (a, b, c : UNSIGNED (1023 downto 0)) return UNSIGNED is VARIABLE...

Count Edges over specific Period of Time in VHDL


vhdl,counter,reset,encoder
For speedmeasurement of an electric motor I would like to count the amount of rising and falling edges of an encoder-input in a time-intervall of 10ms. To do this I have implementet a clock divider for my 40 MHz Clock as follows: entity SpeedCLK is Port ( CLK : in...

Logic synthesis from an arbitary piece of code


logic,vhdl,verilog,synthesis
I have completed on a project making physical logic gates and am now looking for a way to turn an arbitrary program into some series of logic gates so I can use them. I need a program that can take some arbitrary function (say f= x^2 -1) directly into some...

VHDL audio sample volume control


audio,vhdl
I was searching a lot about this problem, but I cant find anything usefull... The problem is, Im making echo efect on FPGA chip.. I have everything prepared, like BRAM for delay, input, output with delay, but I can't find out, how to change volume of output which is coming...

Object is used but not declared?


vhdl,quartus-ii
I have the following VHDL code, its a entity of a project: library ieee; use ieee.std_logic_1164.all; library work; use work.typedef.all; entity uc is port(faaaa: in std_logic_vector(15 downto 0); phi: in std_logic; isDirect,isRam,jmp,store,NarOut,arpOut:out std_logic); end entity uc; architecture b8 of ua is signal instt : std_logic_vector(15 downto 0); signal bit7: std_logic;...

Dynamic Arrray Size in VHDL


vhdl,ram,xilinx,vivado
I want to use dynamic range of array , so using "N" for converting an incoming vector signal to integer. Using the specifc incoming port "Size" gives me an error, while fixed vector produces perfect output. architecture EXAMPLE of Computation is signal size :std_logic_vector (7 downto 0); process (ACLK, SLAVE_ARESETN)...

Expression out of bounds on MATLAB with HDL coder app


arrays,matlab,loops,vhdl,hdl
I try to get the VHDL code corresponding to my simulation on MATLAB with HDL coder app, but I get a first error at the line 25 when I build the MATLAB code on the HDL coder app: Index expression out of bounds. Attempted to access element 15. The valid...

Process evaluated too many times


vhdl,fpga
I have a simple design where I read incoming bytes from an RS-232 port and later "parse" them. I tried to divide this into 2 processes: first one receives bits from the serial port and tries to frame them - if it succeeds, it assigns the result to a signal...

4-bit Shift register with flip flop


vhdl,flip-flop,shift-register
I want to build a 4-bit shift register using D FlipFlop , but I don't understand this diagram. This code is given to me for shift register ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable : IN STD_LOGIC; Sin : IN STD_LOGIC; Clock : IN...

Signal current cannot be synthesized, bad synchronous description


vhdl,fpga
I have a error while Synthesize this code in Xillinx. This error is: Analyzing Entity in library (Architecture ). ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description. entity Parking is port( A, B ,reset: in std_logic; Capacity : out std_logic_vector(7 downto 0)); end Parking; architecture...

Random Generator using UNIFORM


vhdl,uniform
I am trying to generate a random number for a little game and I tried to use the UNIFORM function from the package MATH_REAL. I get a value when I test my code, but it never changes. I tried to make the code happen at every rising_edge but it didn't...

Warning about getting “X”es for 4-valued logic VHDL


vhdl
I am getting a warning that an arithmetic operation have X so the result is will always be X, although I am initializing my signals to 0s. Can anyone help? N.B. I am getting X for Z_count and RC_count_var --RC counter LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; Entity RC_counter2...

Behavioral into FlipFlop Structural


process,vhdl,behavior,flip-flop
In this code, when reset equals 1 the s becomes 1000 and when reset equals 0 the s becomes 0100 then 0010 then 0001 and it starts all over again with 1000 as the start value, only if the clock is up. library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock_behav...

VHDL clock divider flips between 0 and X every clk cycle


vhdl,clock,digital-design
I'm starting out trying to learn VHDL after doing a little bit of Verilog. This is my attempt at creating a clock divider: (largely taken from Making a clock divider) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity clock_192 is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; clk_out...

Synthesizable multidimensional arrays in VHDL


arrays,multidimensional-array,vhdl
I need to use multidimensional arrays to represent matrices in my design. I have tried the two available options: Declaring array of arrays type t11 is array (0 to c1_r2) of std_logic_vector(31 downto 0); type t1 is array (0 to r1) of t11; --r1*c1_r2 matrix Multidimensional arrays. type matrix is...

How to assign pins to natural type of ports in Xilinx


vhdl,fpga,xilinx
How can I assign natural types of ports to pins in XILINX UCF file? Generic ( nr_ro : natural := 32 ); Port ( clk_i : in STD_LOGIC; rst_i : in STD_LOGIC; sel1_i : in natural range 0 to nr_ro-1; sel2_i : in natural range 0 to nr_ro-1; bit_o :...

AXI4 (Lite) Narrow Burst vs. Unaligned Burst Clarification/Compatibility


vhdl,hdl
I'm currently writing an AXI4 master that is supposed to support AXI4 Lite (AXI4L) as well. My AXI4 master is receiving data from a 16-bit interface. This is on a Xilinx Spartan 6 FPGA and I plan on using the EDK AXI4 Interconnect IP, which has a minimum WDATA width...

Module without an EN - VHDL


vhdl,fpga
I've a module that when I don't use it, it must go to reset state so I don't need a moduleEN. So, a module like this: process(clock, reset) begin if reset = '0' then elsif rising_edge(clock) then end if; It's correct for a synthesizer? Or it's better: process(clock, reset) begin...

verilog $readmemh takes too much time for 50x50 pixel rgb image


verilog,fpga,system-verilog,quartus-ii
I am trying to compile a verilog code for FPGA programming where I will implement a VGA application. I use QuartusII and Altera. I am trying to use readmemh properly for acquiring a picture pixel by pixel. For now, I have converted a picture into rgb texts using matlab. Each...

Others => '1' statement in Verilog


vhdl,verilog
I have used VHDL all my life and only been using Verilog for a short time, I have to create a logic in Verilog for a very large array and assign it to 1 or 0 depending on the condition of an input. Here is my VHDL code if (data_track...

how do i initialize a std_logic_vector in VHDL?


vhdl,hdl,xilinx-ise
i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test is type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0); signal ram : ram_type; ram(0) := "0010000000000100"; ram(1) := "0001000000000101"; ram(2) := "0011000000000110"; ram(3) := "0111000000000001"; ram(4) := "0000000000001100"; ram(5)...

importing VHDL packages to SV from libraries other than WORK


vhdl,system-verilog,assertions
I have a VHDL module that is compiled to a library, say, LIB_A. The module has ports that are records, the corresponding type is defined in a package that is also compiled into LIB_A. I would like to write some assertions for the module and check them using OneSpin. At...

VHDL My timer don't work


vhdl
I have a 25MHz clock in my FPGA and I would like to make a timer which returns '1' when it counts for 60 seconds. But I have two problems: I don't understand why my outpout signal "count_sortie" is undefined in Vivado when I simulate it. To force to define...

What does it mean whe you have: case state is when vale1 => state <= value2 in vhdl?


vhdl
This line of code gets me confused. I don't get how it works, I know => and <= are assigning symbols, but why 2 assignments to the same thing?

Write an inout Port in a testbench


vhdl
I am currently working on a project where I want to implement a bidirectional bus. For this project I was given an entity that I should not edit. This entity has two inout ports (sda and scl). I now want to write from the TestBench to the entity through the...

How to get rid of scale factor from CORDIC


math,vhdl,fpga,rtl,cordic
From CORDIC, K_i = cos(tan^-1(2^i)). As I know the K is approached 0.607xxx. How do I approach to 0.607xxx? Also does it mean that I can use 0.607xxx instead of cos(tan^-1(2^I))? I am citing from this article. I am trying to implement hyperbolic tanh function. And so far I understand...

CRC Generator(sender) and Checker(receiver) - parallel implementation VHDL


vhdl,crc
I have generated CRC generator VHDL code for parallel realization from the following website Sigmatone. The polynomial is 100011101 (0x1D) and data width is 16 bits. Here is the code: -- ######################################################################## -- CRC Engine RTL Design -- Copyright (C) www.ElectronicDesignworks.com -- Source code generated by ElectronicDesignworks IP Generator (CRC)....

How to “sample” a value in VHDL?


case,vhdl,counter
So I have a modulo counter going from 1->15, then looping back around constantly in a seperate entity. I would like to, in a case statement depending on some outputs, sample this value on the rising_edge of a clock, but only do it once, otherwise the value will be constantly...

How to get a rgb picture into FPGA most efficiently, using verilog


image,verilog,fpga,vga,quartus-ii
I am trying to write a verilog code for FPGA programming where I will implement a VGA application. I use Quartus II and Altera DE2. At the moment, my aim is to get a 640x480 rgb image during compilation (method doesn't matter as long as it works and is efficient)....

I cannot get the Xilinx uartlite IP to work


vhdl,verilog,fpga,xilinx,vivado
Im attempting to use the Xilinx uartlite 2.0 IP with an AXI4-lite interface to transmit a byte without a microblaze processor. Unfortunately, all the ready signals remain low after I set the data and valid signals and the tx signal never transmits. I've included my simulation results. any ideas? ...

VHDL average of Array through for loop


arrays,for-loop,vhdl,moving-average
I have an Array of X Integer values in VHDL declared as a variable inside a process. I would like to calculate the average of all Values in a for loop. If I write it out for 3 Values manually everything works fine (tested on hardware): entity MyEntity is Port(...

VHDL: (vcom-1136: std_logic_vector undefined)


syntax,vhdl
Getting a seemingly unexplainable syntax error saying that std_logic is undefined, even when it compiles earlier in the code! The first error occurs at the beginning of the entity, or line 37. I believe it has something to do with creating my own package but this is something I have...

Multliplication of std_logic_vector with Floating Point


floating-point,vhdl,fixed-point
I have 32 bit std_logic_vector signal and want to multiply it by floating point . e.g signal Input : std_logic_vector (31 downto 0 ); signal number = 0.2 ; signal Output: std_logic_vector (31 downto 0 ); Output <= 0.2 * Input ; What can be the best solution to do...

RAM to read/write in VHDL


vhdl
I'm trying to use RAM in order to read/write. My address is an integer value and it should be a memory of integers. This is my code below but i keep getting an error. This is from my data path where the address selection is from a register of integers....

Best way to modify strings in VHDL


vhdl
I'm currently writing a test bench for a VHDL design I made and I need to write a message to a text file. The message is of the format [instance_name];[simulation_time] (i.e. U0;700 ns) and the filename must be [instance_name].log. Getting the instance name and simulation time is no problem, but...

VHDL: Convert String to Std_Logic_Vector


string,entity,vhdl,sha
I'm writing a sha-256 hash function in VHDL and it takes in a String. I need to convert this string to a std_logic_vector of bits. So, I must somehow extract the bits from the characters of the String, but I'm not sure of the best way. As far as I...

With the MESI protocol, a write hit also stalls the processor, right?


caching,architecture,multiprocessing,vhdl,mesi
I'm doing a project that is to implement a dual-processor system with some kind of cache coherency (for which I chose MESI) in VHDL. I just want to confirm this one thing: a write-hit on a shared cache line should cause the cache controller to send invalidation messages on the...

Why do I get no output at my VHDL multiplier?


vhdl,xilinx
I am trying to make a 4 bit multiplier. Here is my top level design: And here are the two modules: However when I try to simulate this I get no output. My testbench: ARCHITECTURE behavior OF sim3 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT multiplicator...

Power and timing reports of two different vhdl designs


performance,report,vhdl,timing,area
Let's suppose I have two circuits (described in vhdl), the first one performs the following algorithm in loop(pseudo code): C<=A+B; D<=C+F; RES <= D; I represent this algorithm applying the Finite State Machine(FSM) logic. Thus: State1:C<=A+B; out_ready<='0';--the result is not ready yet nextstate<=State2; State2:D<=C+F; nextstate<=S_out; S_out: RES<=D; out_ready<='1';--the result is...

VHDL modulo 2^32 addition


overflow,vhdl,sha
I am working on a VHDL implementation of the SHA-256 hash function. I have some 32-bit unsigned signals defined as such: SIGNAL a, b : UNSIGNED (31 downto 0); Within the specifications of the SHA-256 algorithm, it says addition must be performed modulo 2^32 in order to retain the 32-bit...

Leon v3 ise-prog-prom error: impact:2070


vhdl,xilinx
I have the following error while executing the command ise-prog-prom to synthesize the vhdl on the platform : error:impact:2070 There are only 0 devices on the chain. Position 1 does not exists. I have tried to look online for some answers but I've had no luck so far. Does anyone...

LATCH Primitive disables outputs?


vhdl,synthesis,quartus
So I understand the concept of a latch, but I'm not seeing how I am inferring one here as my else condition should cover all the possible paths through this process. Quartus is telling me it is disabling the greenLEDS and redLEDs because of LATCH primitive, as well as there...

Reset output after run


vhdl,bcd
I'm working on a small project to learn VHDL. Currently I'm working on a BCD converter (converting a binary to its BCD number). But I got stuck when implementing the testbench. It doesn't reset the output after the patterns got applied. My VHDL code of the entity: library ieee; use...

Query on VHDL generics in packages


vhdl
I have written a simple VHDL code to add two matrices containing 32 bit floating point numbers. The matrix dimensions have been defined in a package. Currently, I specify the matrix dimensions in the vhdl code and use the corresponding type from the package. However, I would like to use...