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Why do I get no output at my VHDL multiplier?

vhdl,xilinx
I am trying to make a 4 bit multiplier. Here is my top level design: And here are the two modules: However when I try to simulate this I get no output. My testbench: ARCHITECTURE behavior OF sim3 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT multiplicator...

CRC Generator(sender) and Checker(receiver) - parallel implementation VHDL

vhdl,crc
I have generated CRC generator VHDL code for parallel realization from the following website Sigmatone. The polynomial is 100011101 (0x1D) and data width is 16 bits. Here is the code: -- ######################################################################## -- CRC Engine RTL Design -- Copyright (C) www.ElectronicDesignworks.com -- Source code generated by ElectronicDesignworks IP Generator (CRC)....

Why use multiple clocks of the same speed in an FPGA design?

vhdl,clock,fpga
I very recently began experimenting with FPGAs. In researching things around the net I've noticed in several places that designs might use multiple separate PLL clocks of the exact same speed. Why is that? One example I will give is this site: Parallella Linux Quick Start They have their FCLK_CLK1...

VHDL average of Array through for loop

arrays,for-loop,vhdl,moving-average
I have an Array of X Integer values in VHDL declared as a variable inside a process. I would like to calculate the average of all Values in a for loop. If I write it out for 3 Values manually everything works fine (tested on hardware): entity MyEntity is Port(...

signal local to process scope

vhdl,grammar,semantics
I have often wondered why a VHDL variable can be declared both on the process as well as the architecture (as shared) level, while a signal can only be declared on the architecture level - even if it is just used in the scope of a single process. Declaring things...

VHDL Type of xxx is incompatible with type of xxx

types,casting,vhdl
Ich have two different types: type signal_4bit_t is record signals_v : STD_ULOGIC_VECTOR (3 downto 0); end record; type signal_8bit_t is record signals_v : STD_ULOGIC_VECTOR (7 downto 0); end record; and I create two Arrays: type Array_signal_4bit_t is array (0 to 2) of signal_4bit_t; type Array_signal_8bit_t is array (0 to 2)...

Design a shift register in VHDL

loops,vhdl,shift
I try to design a bch code as a shift register, so I have this schematic: (clickable) And I made a VHDL code in Altera Quartus to design this shift register with loops, the compilation works but it doesn't make the expected result during the simulation in ModelSim (no output)....

VHDL clock generator with different speeds using button

button,vhdl,debouncing
I am new to VHDL and currently working on a clock generator that generates two different clock speeds. Everything is working, except the switch between the slow and fast speed_status. There seems to be a problem with the "speed button" because sometimes I have to press it more than once...

Multiple behaviours for single entity

testing,process,entity,vhdl
I wrote a VHDL Testbench which contains the following : Lots of signal declarations UUT instantiations / port maps A huge amount of one-line concurrent assignments Various small processes One main (big) process which actually stimulates the UUT. Everything is fine except the fact that I want to have two...

How can I design VHDL modal in the following details?

unit-testing,vhdl,xilinx
Design VHDL model of a functional unit called sign-extender unit used in some processors. Input of this unit is 4-bit signed binary number and output is 8 bit signed binary number. The unit preserves magnitude and sign of the number. Here is my code and it doesn't work. I'm beginner....

4-bit Shift register with flip flop

vhdl,flip-flop,shift-register
I want to build a 4-bit shift register using D FlipFlop , but I don't understand this diagram. This code is given to me for shift register ENTITY shift4 IS PORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Enable : IN STD_LOGIC; Sin : IN STD_LOGIC; Clock : IN...

Or Reduce An Array of Vectors

vhdl
Needs to be placed on a real board, so will have to synthesize. Using an old VHDL, libraries included: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.std_logic_misc.all; Some signals: type my_array is array (N-1 downto 0) of std_logic_vector(31 downto 0); signal enable : my_array; signal ored_enable: std_logic_vector(31 downto 0); Signals...

Multliplication of std_logic_vector with Floating Point

floating-point,vhdl,fixed-point
I have 32 bit std_logic_vector signal and want to multiply it by floating point . e.g signal Input : std_logic_vector (31 downto 0 ); signal number = 0.2 ; signal Output: std_logic_vector (31 downto 0 ); Output <= 0.2 * Input ; What can be the best solution to do...

Using functions in VHDL for synthesis

function,vhdl,synthesis
I do use functions in VHDL now and then, mostly in testbenches and seldom in synthesized projects, and I'm quite happy with that. However, I was wondering if for projects that will be synthesized, it really is a smart move (in terms of LE use mostly?) I've read quite a...

FPGA reached the limit of USB WireIns

vhdl,xilinx,spartan
I'm programming a Xilinx Spartan-6 on an OpalKelly implementation for my master thesis at university. To by precise, this is the FPGA I'm working on (XEM6010-LX45): https://www.opalkelly.com/products/xem6010/ It is mounted on a board that has to acquire multiple signals (8+), process them and generate multiple ones (16+) to close some...

Accessing a signal in both structural and behavioural architecture

architecture,signals,vhdl,counter
I have defined the structural architecture of a module e.g. architecture structural of my_entity is signal counter : integer := 0; begin MODULE port map(......count => counter.....); --this is an inout port end structural; I would like to implement a counter which is incremented based on a change in an...

VHDL Component Port Mapping Issues

vhdl
I am new to dealing with using COMPONENTS in VHDL and I understand how to port map simple things like slowing down a clock, however I have built a sequence dtetctor that seems to work well, but I want to have its' output trigger an input in my LCD write...

Leon v3 ise-prog-prom error: impact:2070

vhdl,xilinx
I have the following error while executing the command ise-prog-prom to synthesize the vhdl on the platform : error:impact:2070 There are only 0 devices on the chain. Position 1 does not exists. I have tried to look online for some answers but I've had no luck so far. Does anyone...

VHDL: Trouble combining entities (components)

vhdl,quartus
Me again! I wrote something SUPER simple in order to demonstrate how entities come together. However, I'm having trouble figuring out why the output of the combined entities never assumes any value (other than U). Here's the code (its super simple, I promise!) library ieee; use ieee.std_logic_1164.all; entity OR_LOGIC is...

If statement using vhdl

if-statement,vhdl,fpga,xilinx
I am designing counter using vhdl using planahead software, anyway I am using if statment but it gave many errors . the purpose of the counter is to count Ascending/Descending from 1 to 10 and the opposite. In case of Ascending I reset the out when it get to 9...

Behavioral into FlipFlop Structural

process,vhdl,behavior,flip-flop
In this code, when reset equals 1 the s becomes 1000 and when reset equals 0 the s becomes 0100 then 0010 then 0001 and it starts all over again with 1000 as the start value, only if the clock is up. library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock_behav...

Connect carry out to carry in for adder/subtractor in structural VHDL

vhdl
So I have the following VHDL code to implement an Nbit adder/subtractor using only a 2:1 mux, an inverter (flips bit), and a full adder. I am having issues connecting the carry out of an adder to the next ones carry in while having the first adder have a carry...

How to get rid of scale factor from CORDIC

math,vhdl,fpga,rtl,cordic
From CORDIC, K_i = cos(tan^-1(2^i)). As I know the K is approached 0.607xxx. How do I approach to 0.607xxx? Also does it mean that I can use 0.607xxx instead of cos(tan^-1(2^I))? I am citing from this article. I am trying to implement hyperbolic tanh function. And so far I understand...

VHDL audio sample volume control

audio,vhdl
I was searching a lot about this problem, but I cant find anything usefull... The problem is, Im making echo efect on FPGA chip.. I have everything prepared, like BRAM for delay, input, output with delay, but I can't find out, how to change volume of output which is coming...

Process evaluated too many times

vhdl,fpga
I have a simple design where I read incoming bytes from an RS-232 port and later "parse" them. I tried to divide this into 2 processes: first one receives bits from the serial port and tries to frame them - if it succeeds, it assigns the result to a signal...

generic adder “inference architecture”: simulation error

vhdl,xilinx,modelsim,inference
So, I have to create a generic N-bit adder with carry in and carry out. I have made two fully working architectures so far, one using the generate function and one using the rtl description as follows: entity: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder_n is generic (N: integer:=8);...

Can signals be used instead of hard coding values multiple times?

vhdl,fpga,modelsim,quartus
I'm a student learning VHDL and have a pretty basic question. I've read that signal assignments don't take place immediately. So the following would not work as expected: x <= y; z <= not x; So I understand that assignments are not immediate / don't happen sequentially, but I have...

VHDL: Why is output delayed so much?

vhdl,hdl,quartus
I'm learning VHDL in order to describe and demonstrate the work of a superscalar-ish pipelined CPU with hazard detection and branch prediction, etc. I'm starting small, so for practice I tried making a really simple "calculator" design, like this: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_signed.all; entity calculator is...

With the MESI protocol, a write hit also stalls the processor, right?

caching,architecture,multiprocessing,vhdl,mesi
I'm doing a project that is to implement a dual-processor system with some kind of cache coherency (for which I chose MESI) in VHDL. I just want to confirm this one thing: a write-hit on a shared cache line should cause the cache controller to send invalidation messages on the...

Convolution of signals using VHDL

signals,signal-processing,vhdl,modelsim
I have been working on implementing convolution operation using VHDL in MultiSim Student PE Edition. The following code compiles successfully, however When I click Simulate i am getting the following error: # vsim # Start time: 10:32:20 on Apr 26,2015 # Loading std.standard # ** Error: (vsim-13) Recompile work.convolution because...

SPI interface works in simulation but not on actual hardware

vhdl,fpga,xilinx
I am trying to send multiple bytes on the SPI bus during the transmit window. Initially I am acquiring data from the flash ADC when the input pulse is high, then calculating its average and transmitting each average value sequentially on the SPI bus. I got the SPI vhdl module...

Index value 0 to 8 could be out of prefix range 1 to 8 - VHDL

vhdl,synthesizer
In my code I'm defining this vector: Data: in std_logic_vector(1 to 8); So I have an input 0:7 and I solve a counter problem when it reach 0. But my Synthesizer give me this warning: Index value 0 to 8 could be out of prefix range 1 to 8 It...

GHDL: no function declarations for operator “and”

vhdl,logical-operators,ghdl
Here is my stripped example: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity queue is port( reset: in std_logic; input_ready: out std_logic ); end entity; architecture reference of queue is signal queue_size: unsigned(15 downto 0); begin process begin input_ready <= (reset = '0') and (queue_size < 1024); end process; end architecture;...

Apply same operation to every byte in array

vhdl
I have a large array of 2 bits elements. I access these elements one after another at every clock cycle changing the value of the 2 bits depending on the inputs of my design. Now, after having accessed them all, I would like to set at a certain value (let's...

If statement using vhdl-counter

if-statement,vhdl,fpga
It'z DFF counter counts from 0 to 10, and from 10 to 0. There z switch to switch between Ascending/Descending. On of the guys in this website helped me to solve the if statement problem but it looks itz not allowed to use it outside the process , si if...

importing VHDL packages to SV from libraries other than WORK

vhdl,system-verilog,assertions
I have a VHDL module that is compiled to a library, say, LIB_A. The module has ports that are records, the corresponding type is defined in a package that is also compiled into LIB_A. I would like to write some assertions for the module and check them using OneSpin. At...

Multiplication by power series summation with negative terms

vhdl,verilog,fpga,vlsi
How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again. For example 0.3545 = 2^-2 + 2^-4 + ... I have...

FIFO error: can't find control signal - VHDL

vhdl,fpga,fifo
I've found a VHDL FIFO code and tryed to modify it to use with two different clocks, one for write and one for read. I've tryed the code and seems to work in simulation, but when I try to synthesize it I get this error: "Can't find control signal for...

RAM to read/write in VHDL

vhdl
I'm trying to use RAM in order to read/write. My address is an integer value and it should be a memory of integers. This is my code below but i keep getting an error. This is from my data path where the address selection is from a register of integers....

How to define sum result's width?

vhdl
I have few unsigned, 8bits-wide number that i need to add/subtract together. Below the example: h_tmp <= signed(r4(calc_cnt - 2) + r4(calc_cnt - 1) + r4(calc_cnt) + r4(calc_cnt + 1) + r4(calc_cnt + 2) - r2(calc_cnt - 2) - r2(calc_cnt - 1) - r2(calc_cnt) - r2(calc_cnt + 1) - r2(calc_cnt...

near “when”: syntax error in VHDL

syntax-error,vhdl,tri-state-logic
I'm trying to write some code to simulate a circuit with two tri-state buffers and a pull-up resistor in VHDL. Below is my code: library ieee; use ieee.std_logic_1164.all; entity PullUpResistor is port ( A, S, B, T : IN std_logic; -- select one of these four inputs TriOut : OUT...

Reset output after run

vhdl,bcd
I'm working on a small project to learn VHDL. Currently I'm working on a BCD converter (converting a binary to its BCD number). But I got stuck when implementing the testbench. It doesn't reset the output after the patterns got applied. My VHDL code of the entity: library ieee; use...

VHDL Testbench over simulate

vhdl,testbed
Why should I create a testbench/testbed in VHDL? Isn't it just as good to sit and manipulate the signals in the simulator to ensure that the VHDL code behaves correctly?

Count Edges over specific Period of Time in VHDL

vhdl,counter,reset,encoder
For speedmeasurement of an electric motor I would like to count the amount of rising and falling edges of an encoder-input in a time-intervall of 10ms. To do this I have implementet a clock divider for my 40 MHz Clock as follows: entity SpeedCLK is Port ( CLK : in...

VHDL simulation stuck in for loop

loops,vhdl,multiplication
I'm doing simulation testing for some VHDL I wrote and when I run it in ModelSim it gets stuck. When I hit 'break' it has an arrow pointing to the For loop in the following function: function MOD_3 (a, b, c : UNSIGNED (1023 downto 0)) return UNSIGNED is VARIABLE...

How to determine if more than one bit in an STD_LOGIC_VECTOR is set in VHDL

vhdl,bit
I am wondering how I can determine if more than one bit of a four-bit STD_LOGIC_VECTOR is set to '1'. e.g if it is "1001" or "1100" or "1111". I am writing a program where I have to set an error signal to '1' if I get more than one...

2's compliment input and using vhdl library for signed input

vhdl,fpga,xilinx
My input data is 2's compliment and I designed the input is signed number and the all of operation is used signed number,the library i used ieee.numeric_std.all, but when i do ‘+’ an error occurred "found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"". So...

Query on VHDL generics in packages

vhdl
I have written a simple VHDL code to add two matrices containing 32 bit floating point numbers. The matrix dimensions have been defined in a package. Currently, I specify the matrix dimensions in the vhdl code and use the corresponding type from the package. However, I would like to use...

Object is used but not declared?

vhdl,quartus-ii
I have the following VHDL code, its a entity of a project: library ieee; use ieee.std_logic_1164.all; library work; use work.typedef.all; entity uc is port(faaaa: in std_logic_vector(15 downto 0); phi: in std_logic; isDirect,isRam,jmp,store,NarOut,arpOut:out std_logic); end entity uc; architecture b8 of ua is signal instt : std_logic_vector(15 downto 0); signal bit7: std_logic;...

How do I make a 16 bit Adder-Subtractor with Overflow detection using VHDL?

vhdl
I am using ModelSim to implement a 16 bit adder subtractor with overflow detection. This is what I have so far. I am not sure how to implement a subtractor into the adder. I know it has to do with the two's complement but I don't know how to do...

LATCH Primitive disables outputs?

vhdl,synthesis,quartus
So I understand the concept of a latch, but I'm not seeing how I am inferring one here as my else condition should cover all the possible paths through this process. Quartus is telling me it is disabling the greenLEDS and redLEDs because of LATCH primitive, as well as there...

Ambiguous type in infix expression VHDL

vhdl,modelsim
I'm getting the following error in ModelSim: Error: [..]/test1_toVectorAlignment_rtl.vhd(40): Ambiguous type in infix expression; t_RAMXx8 or ieee.std_logic_1164.STD_LOGIC_VECTOR. ARCHITECTURE rtl OF test1_toVectorAlignment IS type t_RAMXx8 is array (natural RANGE <>) of std_logic_vector(7 downto 0); signal RAM28x8: t_RAMXx8(0 to 27); BEGIN ... currentIq<=unsigned(RAM28x8(5)(4 downto 0) & RAM28x8(4)); ... END rtl; Entity declaration:...

VHDL: Convert String to Std_Logic_Vector

string,entity,vhdl,sha
I'm writing a sha-256 hash function in VHDL and it takes in a String. I need to convert this string to a std_logic_vector of bits. So, I must somehow extract the bits from the characters of the String, but I'm not sure of the best way. As far as I...

Warning about getting “X”es for 4-valued logic VHDL

vhdl
I am getting a warning that an arithmetic operation have X so the result is will always be X, although I am initializing my signals to 0s. Can anyone help? N.B. I am getting X for Z_count and RC_count_var --RC counter LIBRARY ieee ; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; Entity RC_counter2...

Best way to modify strings in VHDL

vhdl
I'm currently writing a test bench for a VHDL design I made and I need to write a message to a text file. The message is of the format [instance_name];[simulation_time] (i.e. U0;700 ns) and the filename must be [instance_name].log. Getting the instance name and simulation time is no problem, but...

Hello,I am new to VHDL programming please help me out with these errors

if-statement,vhdl,finite-state-machine
I don't know why its showing error although syntax seems to be right. I'm t rying to program sramctl where address adds_in is input address and sram_adds output address I am just mapping the address and have not consider the data bus. library IEEE; use IEEE.std_logic_1164.all; entity sramctrl is port(clk,adsn,blastn,lwdrn,lhold:in...

Dynamic signal creation in VHDL and solution of VHDL error: Syntax error near “process”

vhdl
I'm new to the world of VHDL and I'm getting this error saying Syntax error near process. I checked for the solutions and found that there may be a missing end if statement but in my code I'm not having that problem. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.ALL; USE ieee.std_logic_arith.ALL;...

VHDL integer range inclusive? Difference in FPGA vs. simulation

vhdl,fpga,modelsim,altera
I'm new to FPGAs. I've been doing some simple tests and I found an issue I don't fully understand. I have a 50MHz clock source. I have a signal defined as: SIGNAL ledCounter : integer range 0 to 25000000 := 0; When the ledCounter reaches 25,000,000 I toggle an LED...

VHDL My timer don't work

vhdl
I have a 25MHz clock in my FPGA and I would like to make a timer which returns '1' when it counts for 60 seconds. But I have two problems: I don't understand why my outpout signal "count_sortie" is undefined in Vivado when I simulate it. To force to define...

How to “sample” a value in VHDL?

case,vhdl,counter
So I have a modulo counter going from 1->15, then looping back around constantly in a seperate entity. I would like to, in a case statement depending on some outputs, sample this value on the rising_edge of a clock, but only do it once, otherwise the value will be constantly...

Arrays as buffer VHDL

vhdl,fpga
I need to create a FIFO buffer in VHDL. I need to use a 2 dimensional array to storage data like (number of data)(n-bit data). If I create a single "big" array that storage for example 1000 entrys. Every new data clock I storage one slot. And every output data...

Signal current cannot be synthesized, bad synchronous description

vhdl,fpga
I have a error while Synthesize this code in Xillinx. This error is: Analyzing Entity in library (Architecture ). ERROR:Xst:827 - "C:/Xilinx92i/Parking/Parking.vhd" line 43: Signal current cannot be synthesized, bad synchronous description. entity Parking is port( A, B ,reset: in std_logic; Capacity : out std_logic_vector(7 downto 0)); end Parking; architecture...

VHDL modulo 2^32 addition

overflow,vhdl,sha
I am working on a VHDL implementation of the SHA-256 hash function. I have some 32-bit unsigned signals defined as such: SIGNAL a, b : UNSIGNED (31 downto 0); Within the specifications of the SHA-256 algorithm, it says addition must be performed modulo 2^32 in order to retain the 32-bit...

How to set a value at moduleEN - VHDL

vhdl,counter
I've this code: library IEEE; use IEEE.std_logic_1164.all; entity Controller is port ( CLK : in std_logic; OutENABLE : out std_logic_vector (2 downto 0); ModuleRESET : in std_logic; ModuleENABLE : in std_logic ); end Controller; architecture Controller_archi of Controller is signal Counter : integer range 0 to 4200 := 0; begin...

Force signal from testbench

vhdl,modelsim
The Problem In my design there is a counter used for delays. For simulation purposes I would like to cap it's maximum value witout editing any of the production code. This is done in order to speed up the simulation. What I've tried I wanted to check if it exceeds...

running a 3 to 7 Decoder using a counter

vhdl,hdl,cadence
I am trying to run my 3 to 7 decoder using the inputs coming from my counter ,all the individual codes run fine but the structural code is giving up some error This is the program for my counter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity counter is port(clk ,...

How to assign pins to natural type of ports in Xilinx

vhdl,fpga,xilinx
How can I assign natural types of ports to pins in XILINX UCF file? Generic ( nr_ro : natural := 32 ); Port ( clk_i : in STD_LOGIC; rst_i : in STD_LOGIC; sel1_i : in natural range 0 to nr_ro-1; sel2_i : in natural range 0 to nr_ro-1; bit_o :...

How to compare signal to zero in vhdl?

comparison,vhdl,comparator
I have signal: signal sig: std_logic_vector(N - 1 downto 0); Where N defined in generic, and can be from 16 to 1024. In code i need to compare this to zero: if unsigned(sig) = 0 then do somth end if; But how can I know which delay would be of...

How to execute 'Zoom Fit' in ModelSim/QuestaSim from TCL console?

tcl,vhdl,simulator,modelsim
I'm using ModelSim / Questa-SIM from command line in GUI mode. If ModelSim runs in GUI mode I would like to execute a 'Zoom Fit' from my imported 'wave.do' file. I pass this file to vsim by -do wave.do. Here is the script: add wave * run -all I started...

I cannot get the Xilinx uartlite IP to work

vhdl,verilog,fpga,xilinx,vivado
Im attempting to use the Xilinx uartlite 2.0 IP with an AXI4-lite interface to transmit a byte without a microblaze processor. Unfortunately, all the ready signals remain low after I set the data and valid signals and the tx signal never transmits. I've included my simulation results. any ideas? ...

VHDL is it valid syntax to use string in Generic?

vhdl
I have been using Xilinx tools for a while, and they are perfectly fine with code such as the following: ENTITY Example IS GENERIC( g_Mode : STRING := "Normal"); -- "Normal", "Test" PORT( Clk : IN STD_LOGIC; -- ETC ); END Example; ARCHITECTURE rtl OF Example IS Normal_g : IF...

Logic synthesis from an arbitary piece of code

logic,vhdl,verilog,synthesis
I have completed on a project making physical logic gates and am now looking for a way to turn an arbitrary program into some series of logic gates so I can use them. I need a program that can take some arbitrary function (say f= x^2 -1) directly into some...

Output is always zeros (quotient and remainder) in divider code VHDL

vhdl
Output is always zeros (quotient and remainder) in the code shown below. Even if I assign value of b to remainder,it is giving 0. I have checked for many times but I am not able to understand what the issue is. While compiling, it is showing 2 warnings: - Initial...

How can I merge several Xilinx NGC netlists to an new netlist

vhdl,xilinx,synthesis,xilinx-ise,netlist
I'm using XST (synthesis tool in the Xilinx ISE 14.7 suite) to compile VHDL source files to a netlist (*.ngc file). My code uses several Xilinx IP Cores like ChipScope ILAs for debugging, which are also pre-synthesized as ngc files. I would like to ship only one ngc file to...

Others => '1' statement in Verilog

vhdl,verilog
I have used VHDL all my life and only been using Verilog for a short time, I have to create a logic in Verilog for a very large array and assign it to 1 or 0 depending on the condition of an input. Here is my VHDL code if (data_track...

What does it mean whe you have: case state is when vale1 => state <= value2 in vhdl?

vhdl
This line of code gets me confused. I don't get how it works, I know => and <= are assigning symbols, but why 2 assignments to the same thing?

Writing a Module Which Prevent Overwriting Previous Data in RAM

vhdl,ram
The Problem I have a channel which contains a 512 deep piece of RAM. I have a control block which tells this channel when to write and when to read. When it writes, the write pointer will increase linearly over each clock cycle so long as the capture flag is...

Write an inout Port in a testbench

vhdl
I am currently working on a project where I want to implement a bidirectional bus. For this project I was given an entity that I should not edit. This entity has two inout ports (sda and scl). I now want to write from the TestBench to the entity through the...

how do i initialize a std_logic_vector in VHDL?

vhdl,hdl,xilinx-ise
i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test is type ram_type is array(4095 downto 0) of std_logic_vector(15 downto 0); signal ram : ram_type; ram(0) := "0010000000000100"; ram(1) := "0001000000000101"; ram(2) := "0011000000000110"; ram(3) := "0111000000000001"; ram(4) := "0000000000001100"; ram(5)...

VHDL Clock or Trigger Upscaler Delay

vhdl
I'm developing control algorithms on FPGAs, but I can't claim to be experienced with VHDL. One functionality I needed is a sort of 'Trigger Upscaler', so I want to increase the trigger frequency instead of decreasing it. Here's an explanation: I got a system clk of 50 MHz and got...

pass a dimentional array(2D) to a function VHDL

arrays,types,vhdl,dimensional
I declared a matrix and a signal in my TOP file like this: type scanImage is array (0 to 7,0 to 7) of std_logic_vector(2 downto 0); signal image_matrix : scanImage; Now, I want to send the above signal to a function which calculates number of cells in the matrix which...

16 bit adder using 2 bit adder as component

vhdl,quartus-ii
I am trying to create a 16-bit adder using 2-bit adders as components (which themselves use 1-bit adder as component). However, my code doesn't compile in Quartus II. Can someone help me please? Thank you very much! My project is consisted of 3 files: bit_adder.vhd, add2.vhd and add16.vhd. The error...

Synthesizable multidimensional arrays in VHDL

arrays,multidimensional-array,vhdl
I need to use multidimensional arrays to represent matrices in my design. I have tried the two available options: Declaring array of arrays type t11 is array (0 to c1_r2) of std_logic_vector(31 downto 0); type t1 is array (0 to r1) of t11; --r1*c1_r2 matrix Multidimensional arrays. type matrix is...

8 bit adder subtractor gives a syntax error

vhdl
I am trying to make a generic 8 bit adder subtractor and I wrote all the code bit it gives me an syntax error on Line "big_mode <= (others => mode);".. any help? library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; ENTITY AdderSubtractor IS GENERIC(n: NATURAL :=8); PORT ( Number1...

wait must contain condition clause with until keyword

vhdl
The following VHDL is to be used to test bench a booth multiplier. I keep getting an error on the first wait statement during analysis and elaboration : "wait statement must contain condition clause with until keyword" I have several working test benches written this way (i.e. signal assignment, wait...

How do you access a range of elements of an array in vhdl?

vhdl
signal b_reg, b_next: std_logic_vector(7 downto 0); I want to discard the last bit and concatenate it with another std_logic. Something like: b_next <= rx & b_reg [7 downto 1] ; How do I access the elements from 7 to 1?

signed to std_logic_vector, slice results

vhdl
I need to take the absolute value of a result and I am only interested in the most significant bits. This is what I have done: data_ram_h <= std_logic_vector(abs(signed(resize(r4(calc_cnt - 2), data_ram_h'length) + r4(calc_cnt - 1) + r4(calc_cnt) + r4(calc_cnt + 1) + r4(calc_cnt + 2) - r2(calc_cnt - 2)...

VHDL: How to declare a variable width generic

vhdl
I want to create a VHDL entity with a one generic that changes the width of another generic. entity lfsr_n is generic ( WIDTH : integer := 32; -- counter width POLYNOMIAL : std_logic_vector (WIDTH-1 downto 0) := "1000_0000_0000_0000_0000_0000_0110_0010" ); Unfortunately, it seems I can't reference an earlier defined generic...

VHDL clock divider flips between 0 and X every clk cycle

vhdl,clock,digital-design
I'm starting out trying to learn VHDL after doing a little bit of Verilog. This is my attempt at creating a clock divider: (largely taken from Making a clock divider) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity clock_192 is Port ( clk : in STD_LOGIC; clr : in STD_LOGIC; clk_out...

VHDL: (vcom-1136: std_logic_vector undefined)

syntax,vhdl
Getting a seemingly unexplainable syntax error saying that std_logic is undefined, even when it compiles earlier in the code! The first error occurs at the beginning of the entity, or line 37. I believe it has something to do with creating my own package but this is something I have...

how to do zero padding al the lsb

vhdl
I would like to add zero at the lsb (zero padding). my input is m : IN STD_LOGIC_VECTOR (31 DOWNTO 0); and another vector (lets say a) that his length is changing all the time. I didn't manage doing that by using bitwise "OR" because the length is always not...

Module without an EN - VHDL

vhdl,fpga
I've a module that when I don't use it, it must go to reset state so I don't need a moduleEN. So, a module like this: process(clock, reset) begin if reset = '0' then elsif rising_edge(clock) then end if; It's correct for a synthesizer? Or it's better: process(clock, reset) begin...

Dynamic Arrray Size in VHDL

vhdl,ram,xilinx,vivado
I want to use dynamic range of array , so using "N" for converting an incoming vector signal to integer. Using the specifc incoming port "Size" gives me an error, while fixed vector produces perfect output. architecture EXAMPLE of Computation is signal size :std_logic_vector (7 downto 0); process (ACLK, SLAVE_ARESETN)...

vhdl code understanding, if there is modelsim error about possible infinite loop

vhdl
-- -- VHDL Architecture di_lib.ShiftRegister1.ShiftRegister1 -- -- Created: -- by - 294162.UNKNOWN (VD1210) -- at - 14:19:36 10-04-2015 -- -- using Mentor Graphics HDL Designer(TM) 2010.2a (Build 7) -- LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY WORK; USE WORK.CALC_PKG.ALL; LIBRARY di_lib; USE di_lib.calc_pkg.all; USE ieee.NUMERIC_STD.all; ENTITY ShiftRegister1 IS PORT( d_out : OUT...

Random Generator using UNIFORM

vhdl,uniform
I am trying to generate a random number for a little game and I tried to use the UNIFORM function from the package MATH_REAL. I get a value when I test my code, but it never changes. I tried to make the code happen at every rising_edge but it didn't...

AXI4 (Lite) Narrow Burst vs. Unaligned Burst Clarification/Compatibility

vhdl,hdl
I'm currently writing an AXI4 master that is supposed to support AXI4 Lite (AXI4L) as well. My AXI4 master is receiving data from a 16-bit interface. This is on a Xilinx Spartan 6 FPGA and I plan on using the EDK AXI4 Interconnect IP, which has a minimum WDATA width...

Power and timing reports of two different vhdl designs

performance,report,vhdl,timing,area
Let's suppose I have two circuits (described in vhdl), the first one performs the following algorithm in loop(pseudo code): C<=A+B; D<=C+F; RES <= D; I represent this algorithm applying the Finite State Machine(FSM) logic. Thus: State1:C<=A+B; out_ready<='0';--the result is not ready yet nextstate<=State2; State2:D<=C+F; nextstate<=S_out; S_out: RES<=D; out_ready<='1';--the result is...

Expression out of bounds on MATLAB with HDL coder app

arrays,matlab,loops,vhdl,hdl
I try to get the VHDL code corresponding to my simulation on MATLAB with HDL coder app, but I get a first error at the line 25 when I build the MATLAB code on the HDL coder app: Index expression out of bounds. Attempted to access element 15. The valid...

VHDL Accumulator - Infix errors

vhdl,unsigned,modelsim,nco
I'm trying to create an accumulator to use in an NCO, but getting some strange errors. I'm fairly new to VHDL so any help is appreciated, here's my code: library IEEE; use IEEE.STD_LOGIC_1164.all; -- for std_logic and std_logic_vector use IEEE.NUMERIC_STD.all; -- for unsigned type --------------------------------------------------------------------- -- accumulator entity declaration ---------------------------------------------------------------------...

FPGA: Divide range by fixed number using a look-up table

math,signal-processing,vhdl,fpga,lookup-tables
I have implemented a block in an FPGA which supports hardware multiplication. This block does some division by using hardly any logic elements because it's able to use some internal DSP. This block has to be ported to another design, but here I have 2k less logic elements and no...