FAQ Database Discussion Community


Using a pipe (or) in sed

regex,linux,sed,makefile,make
From a variable $(JS_SOURCES) containing something like " thing.js myapp.mod1.js otherthing.js myapp.mod1.submod.js myapp.othermodule.js " make writes a file containing mod1,othermodule. It works with this code: ./build/modules.txt: $(JS_SOURCES) @echo "$(JS_SOURCES)" | sed -r -e 's/\s\S*myapp\.(\w+)\.js\b/ \1/g' -e 's/\S*\.\S*//g' -e 's/^\s+//' -e 's/\s+$$//' -e 's/\b\s+\b/,/g' > $@ And my question is Why...

Building just one tool from Android source (AOSP)

android,linux,makefile,android-source
Currently I'm using the the AOSP ROM Builder image on Amazon AWS to build Android. The point is, I'm only interested in the external tool grxmlcompile that is built for the host (linux) in the path: aosp/out/host/linux-x86/bin where the source is at aosp/external/srec/tools/grxmlcompile I'm not very familiar with Linux and...

Defining macro function from makefile

c++,c,makefile,macros
Suppose I have following entry in my makefile: ifeq ($(MY_DEBUG),yes) EXTRACXXFLAGS += -DMY_DEBUG=2 endif I am invoking it with make foo MY_DEBUG=yes and now I basically have #define MY_DEBUG 2 for all project files available. Question: Can I define the macro function all over the project this way, without including...

makefile foreach stops at the first iteration

makefile,g++
I have a list of source files to be compiled. I select them from different directories/subdirectories and in the end I have a list. I thought I would use a foreach loop with eval/call/define.The command info works and the first pass of make sees all of them. Here is the...

Installing twitcurl on OS X

c++,osx,twitter,makefile,clang
I am attempting to install twitcurl on OS X and have met with some problems. At first, running make would return the clang error: ld: unknown option: -soname. I looked through the responses from other users with similar problems on OS X and found the following advice: In the makefile,...

How to export directly in a Makefile?

c++,makefile,export
I want to export something directly in my Makefile so I did a rule like this one : export: export LD_LIBRARY_PATH=./smthing/here And then I call this rule in my $(NAME) $(NAME): $(OBJS) $(CXX) -o $(NAME) $(OBJS) $(CXXFLAGS) $(LDFLAGS) $(export) $(OBJS) is a simple rule to convert all my .cpp into...

What's the meaning of ?= in a kernel makefile? [duplicate]

linux,makefile,linux-kernel
This question already has an answer here: Makefile variable assignment 4 answers I've started learning about building external Linux kernel modules, and in the documentation examples of kbuild (here) I've come across the line KDIR ?= /lib/modules/$(shell uname -r)/build which is then used in make -C $(KDIR) M=$(PWD) and...

add dependencies to a library, and add them to a binary which depends on that library

c++,makefile,gnu-make
What I have: I have a non-recursive makefile which searches for module.mk files, and includes them modules := $(shell find . -name module.mk) include $(modules) If I want to create a static library, the module.mk looks like this: $(eval $(call make-lib, test_lib)) Which will find a list of all .cpp...

Merging two Makefiles to build one output

c,makefile
I have a simple OS which has its own makefile to build its floppy as output and the picoc (a tiny c compiler) which also has its own Makefile to built its own executable output file. Now I want to move this picoc to my OS which means I should...

makefile multiple source file compilation rule in one step

gcc,makefile
I have a directory structure as below: Makefile src/ file1.cpp file2.cpp inc/ file1.h file2.h Now I wanted to write a make rule to create a 'objs' directory and put all my objects(.o files) in 'objs' and then build a library out of it. I wanted to do this in one...

Makefile: two different executables taking two overlapping subsets of code

c,makefile
This is my situation, I am trying to write a Makefile for my c program, it has these components -- 2 Headers: src/header1.h src/header2.h N Sources: src/src1.c src/src2.c src/src3.c ... src/srcn.c 2 Mains: src/main1.c src/main2.c main1.c and main2.c takes all the same src*.c and header*.h files, but in a different...

Can Make be made to understand that a/../z and b/../z are the same location?

makefile,make,gnu-make
I have a somewhat large and complex Makefile setup that postprocesses some data files. Overall it work quite well, but I have run into an annoying issue where Make builds the same target many times over under different directory names. As a simple example, consider the Makefile foo : 1/foo...

How to use variable with ':' in a Makefile?

c,makefile
I got a problem when I want to use make, containing a variable linking to my folder. Like this : DIR_ST = I\ \:\ The\ Scared\ Stones SRC_ST = $(DIR_ST)/main.c OBJ_ST = $(SRC_ST:.c=.o) But when I want to compile like this: all : $(ST) $(ST) : $(OBJ_ST) $(CC) $(OBJ_ST) -o...

Bash: for loop in Makefile: unexpected end of file

bash,makefile
I am writing a Makefile, which will list all headers included by a.cpp, b.cpp and c.h files. However, I got the error of unexpected EOF. Similar questions are always caused by the line terminator, like they used CRLF instead of LF for an EOL. However, my Text editor was set...

Required prebuild rule in generic Makefile

c++,makefile,webots
I'm compiling C++ code for Webots (a robotic simulator), by means of makefiles, and I'm using the generic makefile Makefile.include Webots supplies to ease the process. I build by own makefile, set a bunch of required variables and then call that makefile that sets all the necessary rules for compilation....

Generating roll-up with makefile runs even if files don't change

makefile
I am trying to make a roll-up file of all of the generated css. The bin/generateTemplates script handles fetching all the *.less files from their nested directories and generating the rollup in build/gui.css. However, even if none of the files in LESS_FILES changes it still triggers the script to run....

How do I run only some makefile commands as root?

c,makefile,make,install,sudo
I have an install target in my Makefile and wish to run some commands that install shared libraries(requires root permissions) and some that install config files into $HOME/.config Usually I'd just tell the user to run sudo make install, however that results in the config file being installed to /root/.config...

makefile library dependencies - resolve circular dependency

c++,makefile,gnu-make
I am trying to build a feature into my makefile which allows me to specify a list of libraries a particular library depends on This will allow dependants of a library to automatically be rebuilt if that library's dependencies are rebuilt, and also have the dependencies added to the link...

read prompt doesn't print correctly when run within Makefile

bash,makefile
I'm trying to prompt user input but I'm having trouble to get read -p prompt getting printed as expected when run from within a Makefile or a subshell started by a Makefile. Here are my attempts on achieving this without success: test1: @echo '>> before input <<'; \ read -p...

GNU make equivalent to BSD make's $(var:Q)?

makefile,make,gnu-make,bsdmake
BSD make has a :Q variable expansion modifier, documented in the FreeBSD make man page as follows: :Q Quotes every shell meta-character in the variable, so that it can be passed safely through recursive invocations of make. If variable var has value a b\c"d'e$f, then $(var:Q) expands to a\ b\\c\"d\'e\$f...

Eclipse Makefile: Make Variables are skipped

eclipse,makefile,make
I have a project with a Makefile in it, on Unix console it works fine, compiles, builds and I can run the binary at the end. I imported the project into Eclipse workspace and somehow Makefile module of Eclipse cannot build the project now. It gives the following error: g++:...

Fortran: makefile error

makefile,fortran,fortran90
I have a fortran main program called solidsolver.f90, and a module called read_mesh.f90. The module contains two subroutines and is used in the main program. I can compile them manually but not with a makefile. My makefile is named makefile.makefile, and it gives me an error: make: *** No targets...

Unable to understand this piece of code in a makefile

makefile,contiki
I am unable to understand the following piece of code from Contiki-os' native platform's makefile. NM ?= nm OBJCOPY ?= objcopy STRIP ?= strip ifdef WERROR CFLAGSWERROR=-Werror -pedantic -std=c99 -Werror endif CFLAGSNO = -Wall -g -I/usr/local/include $(CFLAGSWERROR) CFLAGS += $(CFLAGSNO) -O Source: https://github.com/contiki-os/contiki/blob/master/cpu/native/Makefile.native#L13-20 It is not the variable assignments that...

Why Bash-in-Makefile expression doesn't work?

bash,makefile,gnu-make
Directly pasted into my shell, the following tries each of the 3 regex and works (see the *.{jpg,png,gis.tif}): for file in ./output/India/*.{jpg,png,gis.tif}; do echo $file; openssl base64 -in $file -out ./output/India/`basename $file`.b64; done; As a makefile process, it fails and returns : task: for file in ./output/India/*.{png,jpg,gis.tif} ; \ do...

non-recursive make constrict targets

makefile
Based on this paper, I'm trying to rework a subset of my build system to be non-recursive. It's actually working pretty well. By default, I have part of my makefile include all the relevant directories via a template: DIRECTORIES = dirA dirB ... etc ... define import_template dir := $(1)...

basic makefile ifeq how to

makefile,make,gnu-make
I am just learning about Makefiles and am having trouble with ifeq. Version = GNU Make 3.82 Here is my simple Makefile: CHECK := 0 CHECK2 := 0 check : @echo "Check=${CHECK}" @echo "Check2=${CHECK2}" ifeq (${CHECK2},${CHECK}) @echo "EQUAL" else @echo "NOT EQUAL" endif Here is the output: Check=0 Check2=0 NOT...

Link target to libraries

makefile,cmake,mingw,cmake-gui
I have a "CMakified" version of CryptoPP and I am using CMake-GUI to create a MakeFile which ming-make could process as shown in the image below. The "MakeFile" creation was successful but when I executed mingw32-make.exe I got below errors at the very end. Linking CXX executable cryptest.exe CMakeFiles\cryptest.dir/objects.a(test.cpp.obj):test.cpp:(.text+0x8e82): undefined...

Autodependency generation in makefiles

makefile,make,gnu-make,makefile-project,multiple-makefiles
I am trying to understand how autodependency is generated in makefiles in the given link, i cannot understand the following piece of code: DEPDIR = .deps df = $(DEPDIR)/$(*F) SRCS = foo.c bar.c ... %.o : %.c @$(MAKEDEPEND); \ cp $(df).d $(df).P; \ sed -e 's/#.*//' -e 's/^[^:]*: *//' -e...

undefined reference to `vtable for implementation' error

c++,build,makefile
I wrote some c++ files and after compiling with out make file it works fine . But when using make file it pop out some errors . My codes are : include directory files : application.h #ifndef APPLICATION_H #define APPLICATION_H #include "employee.h" #include "employee_data.h" #include "employee.h" ...some defintions here... #endif...

math.h not being included even when it is included in makefile

c++,c,makefile,automake
I am trying to build SPRO from http://www.irisa.fr/metiss/guig/spro They use Automake 1.6.2 to generate the makefile. My issue is that when I am trying to make the project I am getting the error "undefined reference to 'sin' " etc. Here is the error image This error is due to the...

What does semicolon-termination inside a Makefile's define directive do?

makefile,make,openwrt
I'm wondering what the semicolons in the following makefile snippet do: define Package/xxsim/CopyLocalFiles $(call cp, files/Adapter20Sim.h, $(PKG_BUILD_DIR)/xxsim); $(call cp, files/Adapter20Sim.cpp, $(PKG_BUILD_DIR)); endef Hooks/Prepare/Post+=Package/xxsim/CopyLocalFiles In case it matters, the makefile is for a custom component (xxsim) in the OpenWRT buildsystem. I would expect that the semicolons are unnecessary, per, e.g., this...

Pattern rule with partial dependency

makefile,gnu-make
I have a makefile with a bunch of .R scripts that create .csv files as output. These files are then used in a python simulation. all: $(FILES) python simulation.py $(FILES): %.csv: %.R Rscript $< This is straightforward. My wrinkle is that one (and only one) of the .R scripts has...

How to run custom commands during `make uninstall` from qmake in QT5?

c++,qt,makefile,qt5,qmake
I have a QT project that installs a service to the system, when running make install. The relevant parts of the .pro file are the following: init.path = /etc/init.d/ init.files = myservicename updaterc.path = /etc/init.d/ updaterc.extra = chmod 755 $$init.files; \ update-rc.d $$init.files defaults 97 03; \ service $$init.files start...

Would GNU Make automatically add extra prerequisite?

c++,build,makefile,make
The following example snippet is from "Managing Projects with GNU Make(3rd edition)" p.21. count_words: counter.o lexer.o -lfl The author says that make will automatically add count_words.o to prerequisite list by implicit rule. Quoted: ..., make identifies four prerequisites: count_words.o (this prerequisite is missing from the makefile, but is provided by...

Makefile Fatal error: can't create obj/calc.o

c,makefile
I'm trying to make a makefile for a simple calculator for a college project. I need it done, and I've searched the web for tutorials and I eventually found this code: IDIR =include CC=gcc CFLAGS=-I$(IDIR) ODIR=obj LDIR=lib SDIR=src LIBS=-lm _DEPS = calc.h DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS)) _OBJ = calc.o libcalc.o...

Git tag name as version in Go via Travis-CI

github,go,makefile,travis-ci
Essentially what I want to do is embed the git tag name (from a github release) to a version string within my GO code. If I use this code; package main import ( "flag" "fmt" ) var version string func main() { var verFlag bool flag.BoolVar(&verFlag, "version", false, "Returns the...

Setting the variables in Makefile target not working as expected

variables,makefile,gnu-make
I have a simple Makefile where I would like to set a variable in one of the targets (so that I can use this variable in other targets). My simple Makefile: VAR=DEFAULT import: echo $@ VAR=$@ echo $(VAR) Output when I run "make import": echo import import VAR=import echo DEFAULT...

make target with multiple extension

makefile,make
How to do the following in gnu make (on mac). I have files with extendion .js and .jsx which needs to go through the build. SRC = $(shell find src -name '*.js' -o -name '*.jsx') LIB = $(SRC:src/%=lib/%) lib/%.js: src/%.js @echo "building $@" above only define the target for *.js...

How to force a full recompilation of all files for every make?

c,makefile
I'm hoping to create a basic makefile template for small-scale C apps. In this scenario, I'm less concerned with performance than clarity and want to recompile everything - All .h and .c files, and third-party .so files. # Constants #=============================================================================== # Specify the C complier CC = gcc # List...

Makefile process all files in one directory, output to another.

makefile,make
How do I set up a Makefile to process all files in one directory, redirecting output to another (one output file per input file)? I have: INPUTS := $(wildcard ./input/*.txt) OUTPUTS := $(patsubst %.out,%.txt,$(wildcard ./input/*.txt)) $(OUTPUTS): $(INPUTS) python process.py $@ > ./output/${@:%.txt=%.out} ... but it keeps regenerating files in ./output...

How to compile fortran code to run without gfortran installed

osx,static,compilation,makefile,fortran
I have downloaded Bellhop, which is an underwater acoustic simulator written in Fortran. It can be found here with the Makefile. Question 1: I would like to know if it is possible to compile Fortran code, including everything needed, so a user without gfortran installed, can run it. I have...

How to specify multiple source files in Makefile.am

c,makefile,autotools,automake
New to using autoconf and automake, I am following this to learn them. I have a question regarding Makefile.am file. For a simple helloworld program below Makefile.am works: AUTOMAKE_OPTIONS = foreign bin_PROGRAMS = helloworld helloworld_SOURCES = hello.c How do we specify multiple source files (if there are multiple source files...

No rule to make target

c,makefile,gnu-make
I am trying to follow this tutorial: http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/ When I am at the last makefile (#5), the "make" can't proceed becasue (error prompt) No rule to make target "obj/hellomake.o", needed by "hellomake". This piece of code tries to compile the sources files and put libs, srcs, objs into respective folders....

Makefile overriding default implicit rule

c++,c,makefile,make
Why this rule cannot override the default implicit rule ? When make is invoked like: make myapp (suppose myapp.c is there). The make runs the default command to build and link the program instead the commands defined in this implicit rule: #... omitted code LCUS=$(LIBS)/libcus.a #... omitted code % :...

Makefile: no rule to make target with variables

c,makefile
I'm trying to write a Makefile that when I add some deps in my application I just have to change DEPS_NAME variable, but something is wrong and I can't figure out what. I know that this is not the only problem with this Makefile, I just started to study this...

Compile a project with C and C++ files separately using gcc and g++?

c++,c,gcc,makefile,g++
I have a project that contains C and C++ files and I created a Makefile to compile this project. Is it possible to have a Makefile that will "separate" the C and C++ files, the C files will be compile with gcc and the C++ files with g++ and create...

gcc make dependency and object simultaneously

gcc,makefile,g++
I am using gcc 4.8.2, and I am trying to build both the object file and the dependency file concurrently. This works: $ g++ -std=c++11 -MP -MD -c foo.cxx -o foo.o $ [ -s foo.d ] && [ -s foo.o ] && echo yay yay However, instead of generating foo.d,...

unrecognized debugging option: 1 [enabled by default]

c,gcc,compiler-errors,makefile,cross-platform
I am writing a cross-platform gtk application for Windows and linux in C. Today I came across the strange compiler error in the title (which I have never seen before). This happens when I build my program in Windows, but not in Linux. When I build it in Windows via...

Cross compile stunnel

linux,makefile,cmake,arm,cross-compiling
I am having difficulties with cross compiling stunnel for an ARM device. Cross compiling OpenSSL was done via this CMake project: http://www.valvers.com/open-software/projects/openssl-cmake/ and it runs successfully on the target device. The CMake toolchain file I use when compiling OpenSSL: SET(CMAKE_SYSTEM_NAME Linux) SET(CMAKE_C_COMPILER /home/elias/toolchains/axotec/3.4.1/bin/arm-linux-gcc) SET(CMAKE_CXX_COMPILER /home/elias/toolchains/axotec/3.4.1/bin/arm-linux-g++) SET(CMAKE_FIND_ROOT_PATH /home/elias/toolchains/axotec/3.4.1/arm-linux...

Makefile targets with same file prefix, several file extensions

makefile,make
I'm writing a makefile that, as part of its operation, downloads and extracts a zipfile containing an ESRI shapefile. Shapefile is a misnomer, because a shapefile is actually a directory containing files named like shape.[shp,dbf,prj,shp.html,shp.xml,sbn,sbx] Is there a way of defining a list of extensions to append to a common...

How to install gem via Makefile if it doesn't exist

ruby,makefile,gem
I'm creating a Makefile for my project: build: sudo gem install sass Any time I build it's asking me for my superuser password. If I remove sudo it will not install at all, but throw an error instead, as I don't have permissions to install a gem. So I came...

Readelf reports program is a shared library instead of executable

c++,makefile,android-ndk,clang
got this strange behaviour with standalone Android NDK r10e Toolchain (built with --toolchain=x86-clang3.6 switch). Environment variables for cross compilation have been set before running makefile, SYSROOT points to Android toolchain location, CXX equals i686-linux-android-clang++. Basically, I have a bunch of cpp files that I would like to compile to Android...

C++ Struct prototyping in separate header file

c++,c,struct,makefile
I am having trouble understanding an answer I saw in another post. It said that it is good practice to define a struct in a separate .h file so it can be used in other files. I think that is great and it solves my current dilemma, however I have...

Makefile: wildcard and patsubst does not change file source names

c,makefile
I am trying to write a Makefile for my project, all the *.c and *.h files are in a folder called src, and the Makefile looks like this -- CC := gcc CFLAGS := -g -Wall -ansi -pedantic -std=gnu99 LDFLAGS := -lm INCLUDES := $(wildcard src/*.h) IFLAGS := $(addprefix -I/,$(INCLUDES))...

Dot in front of variables in make files

makefile,make,gnu-make
I am not able to figure out what does a dot . in front of a variable in makefile does. For e.g.: SOURCEDIRS = . $(PROJECTDIRS) $(TARGET_DIRS_CONCAT) vpath %.c $(SOURCEDIRS) It would be great if someone could tell me. Thanks!...

gcc auto dependency full path

c++,gcc,makefile,g++
I have a simple project - it has a foo.cxx and a bar.h: // bar.h // nothing // foo.cxx #include "bar.h" // nothing else If I include bar.h with ""s, then the dependency file has everything with its full paths: $ g++ -std=c++11 -MP -MMD -MF /home/barry/sandbox/foo.d -c /home/barry/sandbox/foo.cxx -o...

force a script to run at the beginning of a makefile, and display its output

makefile,gnu-make
I have a script which generates a version.h file with various details about the particular build The script runs various commands, such as: readonly VERSION=$(git describe --always --dirty --long --tags) readonly NUM_COMMITS=$(git rev-list HEAD | wc -l | bc) readonly BRANCH=$(git rev-parse --abbrev-ref HEAD) readonly AHEAD_BY=$(git log --oneline origin/${BRANCH}..${BRANCH} |...

What does the following makefile command do? /no-symbols-control-file

makefile,make,gnu-make,binaryfiles,contiki
I cam across the following command in a makefile: %-nosyms.$(TARGET).elf: %.co $(PROJECT_OBJECTFILES) $(INTERRUPT_OBJECTFILES) contiki-$(TARGET).a $(CC) $(CFLAGS) -o $@ $(filter-out %.a,$^) $(filter %.a,$^) $(filter %.a,$^) $(LDFLAGS) Source: Contiki/cpu/arm/stm32f103/Makefile.stm32f103 . Does this command generate no-symbols-control-file? What is the use of a no symbol image file?...

Converting Makefiles to CMAKEList (compilation successful but the program behave differently) [closed]

c++,makefile,cmake
I would like to ask how to convert Makefile to CMAKEList. Currently I can compile CMAKEList. However, the program doesn’t behave like the program generated out of Makefile program. details: 1. This is my Makefile #=========================================================================== # Makefile for behavior_program #--------------------------------------------------------------------------- # [Update log] #=========================================================================== TARGET = PFforAEV0.2.2 CC =...

make: *** No rule to make target 'rm', needed by 'clean.Stop

c++,makefile,make
I am working with cygwin on windows 8.1. I have used the following make file .SUFFIXES : .o .C CFLAGS = -g2 CC =g++ ${CFLAGS} LIBRARIES = -lm .C.o : ${CC} -c $< SOURCE-FILES = sparsegraph.C myvarious.C pairlist.C graphlist.C peo.graph.C choldc.C copy.C metropolis_fns.C likelihood.C metropolis.C OBJECT-FILES = sparsegraph.o myvarious.o pairlist.o...

Dependent C++ project binaries not relinked in Netbeans

c++,netbeans,makefile,make
I've got a two projects in Netbeans. The first a library, and the second an application. The application depends on the library. When I make changes to the library and attempt to run the application the library is rebuilt, however the library and application object files are NOT relinked unless...

Linking with GHC

c,haskell,makefile,ghc,webots
I am following this short tutorial and trying to compile Webots application (written in C) using GHC (Glasgow Haskell Compiler, Version 7.10.1) with following command: ghc --make -no-hs-main -optc-O -I"/Applications/Webots/include/controller/c/" -L"/Applications/Webots/lib/" -outputdir build/release/ advanced_genetic_algorithm_supervisor.c Safe -o advanced_genetic_algorithm_supervisor and getting the following error during the linking phase: Linking advanced_genetic_algorithm_supervisor ... Undefined...

A make rule for verbosity

makefile,make
Typically we have this in a Makefile %.o:%.c $(cc) $(flags) -o $@ -c $< When the amount of flags is huge, I feel better to write this instead %.o:%.c $(info $(cc): $< --> $@) @$(cc) $(flags) -o $@ -c $< However it can be useful to sometime see everything. So...

Makefile with two targets and two languages

c++,c,gcc,makefile
I work with C and C++ and thanks to this answer I was able to compile and run my project. Now I am writing a makefile to spare time. But things are getting complicated : Project structure project makefile client bin src c cc java server ... # Directories #...

Making targets out of computed variables in make

makefile,make
Here is an example that doesn't work say-hello := greeting say-bye := farewell greeting: @echo "Hello" farewell: @echo "Bye" .SECONDEXPANSION: %-guvnah: $$(say-$*) @echo "Target was: $(say-$*)" The command make hello-guvnah Should yield hello Target was: greeting But shows only Target was: greeting ...

Make Immediate Variable Assignment

variables,makefile
I'm having issues with immediate assignment of variables in a make file using := combined with variables assigned with +=. For example: VAR := a VARS += $(VAR) rule1: echo "$(VARS)" VAR := b VARS += $(VAR) rule2: echo "$(VARS)" When I run make, regardless of the rule, it prints...

Nested For loop in makefile

shell,makefile,make
I am trying to loop through the .c files in a specific directory through the makefile. i used the following code, but it seems not working: DIR= Sources \ Sources_2 @for entry in ${DIR} ; \ do \ @for i in $${entry}/*.c ; \ do \ echo "Processing $${i}"; \...

NASM: Makefile for library

assembly,makefile,nasm
I'm having trouble building a makefile for a library in nasm, since it requires that you run nasm with one input file at a time. I have tried with the %.o : %.s thing but I'm probably doing it incorrectly since it's not working. Here is what I have: NAME...

Makefile on different folders

c++,makefile,g++
I know it has already been discussed a lot, but I'm getting a bit crazy and cannot figured it out by myself. I'm trying to learn how to create makefiles, and I'm having problems in defining a makefile for files in different folders. This is what I would like to...

Makefiile with many flags

c++,linux,makefile,linker,intel-mkl
I am trying to learn how a Makefile should look like, when it comes to the flags, especially the linking ones. Here is my Makefile: OBJS = n.o SOURCE = n.cpp # HEADER = there are no header files, so I commented that OUT = test CXX = ../mpich-install/bin/mpic++ FLAGS...

How to write CMakeFile when the code use C++, but called python

python,c++,linux,makefile,cmake
I have a C++ project with a CMakeFile which works ok before. Now i write a new class in C++ but calling python to run. I kown how to write a MakeFile to build the single C++ with python, but what makes me confused is how to write the CMakeFile...

What's the difference between $@ and $1 when there is only one parameter?

makefile,make
There are some C code: apple.c #include<stdio.h> int main(void) { printf("apple\n"); return 0; } Makefile apple: gcc -c $@.c gcc $@.o -o $@ $ make apple and it works perfectly. But if I modify Makefile as: apple: gcc -c $1.c gcc $1.o -o $1 $ make apple It does not...

Makefile : How to runs 2 distinct shells?

node.js,bash,makefile,gnu-make,forever
I use a makefile to store my processes. One of these processes requires a server. Also, my script.make is such : end: server script # runs the 2 other tasks, 1st `server` then `script` script: node ./node_script_with_server_queries.js server : node ./node_modules/.bin/forever ./node_modules/.bin/http-server Then I runs the makefile, is start the...

Why Make doesn't recognize my variable?

makefile
I have a short Make script, which works if I put the Build directory in as a string manually myself instead of as a variable: CC = gcc CFLAGS = -O2 -g -Wall -fmessage-length=0 LDFLAGS = SRCDIR = Src BUILDDIR = Build SRCS = $(SRCDIR)/Main.c OBJS = $(SRCS:.c=.o) LIBS =...

Makefile pattern rules differences

c++,c,makefile
What is the difference between .cpp.o:, .o: and %.o: %.c? Here's a simple Makefile example: CC=g++ CFLAGS=-c -Wall SOURCES=file1.cpp file2.cpp OBJECTS=$(SOURCES:.cpp=.o) EXECUTABLE=dbase $(EXECUTABLE): $(OBJECTS) $(CC) $(OBJECTS) -o $@ #.o: #.cpp.o: %.o: %.c $(CC) $(CFLAGS) $< -o $@ all: $(SOURCES) $(EXECUTABLE) clean: rm -rf $(OBJECTS) $(EXECUTABLE) I noticed that the output...

GNU make - depend only on file existence and not modification time

linux,build,makefile,dependencies,gnu-make
I want to have a makefile in which I have a task a that can only run if a file b exists, but does not need to be re-run if b is updated. How do I do this?

Reading makefiles. Meaning of symbols

linux,makefile
I am trying to learn how to read makefiles and came across this one. My question is referring to the rule with target %.c. On the first command. where it says %.c: %.psvn psvn2c_core.c psvn2c_state_map.c psvn2c_abstraction.c ../psvn2c $(PSVNOPT) --name=$(*F) < $< > $@ What does $(*F) < $ < >...

What's the possible reason that makefile would skip making one executable?

makefile
I try to then execute exact same compilation command for that skipped file and it is being correctly compiled. But when I put it in make file it is just skipped. Every other file is generated.

Makefile not recompiling on header file change

c++,makefile
I have 2 .cpp files : main.cpp A.cpp and few header files in include dir. I am trying to write a makefile that recompiles whenever a header file changes. Now I tried following the method outlines in the example here. However I could not get started. Here is my attempt...

Compilation on linux with defined target

c++,linux,compilation,makefile
I want to compile a project with a Makefile. I have defined target for linux in one of my .h #define LINUX_TARGET (COMPILER_GCC_4_4_1|FAMILY_LINUX|TYPE_X86) ... #ifdef _LINUX_TARGET_ #define __linux__ #define TARGET LINUX_TARGET ... #ifdef __linux__ #define __LINUX__ #endif So in my Makefile I say that, I will use this target: ......

xcode 6.3.2 external build

c++,xcode,makefile,make
I'm trying to compile an existing c++ project, originally developed on linux with gcc. The only external library is GSL (GNU Scientific Library). I have created an external build tool project to use xcode's debugger, but I currently have two issues. 1) When I try to build in xcode it...

Adding debug file to makefile build?

makefile,gnu-make
I have a makefile for a project that I want to be used for debug and release builds. For the debug build I have to include an extra cpp file that holds all the unit tests. I have added a debug option to the makefile and everything seems to work...

make error during building webkitgtk

linux,makefile,cmake,make
I use UBuntu 14.04 LTS. I need to build webkitgtk 2.8.3 Here is an example instruction which I have used: linuxfromscratch When I run sudo make -j8 I get following log: Scanning dependencies of target JavaScriptCore-4-gir Scanning dependencies of target fake-generated-webkitdom-headers [ 0%] Scanning dependencies of target WebKit2-fake-api-headers Scanning dependencies...

Make only uses VPATH on the second run?

c,assembly,makefile
I am trying to compile and assemble, then link, some source files. As far as I can tell, it doesn't tell the linker to use the path in VPATH until I run it the second time. Here's the Makefile: #Makefile for SWS ARMKern CC=arm-linux-gnueabi-gcc LD=arm-linux-gnueabi-ld CFLAGS=-g -Wall -Wextra -std=gnu11 -ffreestanding...

create makefile for static library and executable simultaniously

c,makefile
I have 3 files which should included in static library (file1.c,file2.c,file3.c) and one file which should include the main function (main.c file) and linked to the static library. I would like to create one makefile that create the library and then create the executable. My base makefile is: CC=gcc CFLAGS=-c...

Compile Fortran source with Accelerate Framework (LAPACK and BLAS) [duplicate]

osx,makefile,frameworks,fortran
This question already has an answer here: How to use LDFLAGS in makefile 2 answers I wish to compile Fortran source code which uses functions from LAPACK and BLAS. When I compile a single source code file e.g. gfortran -g -framework accelerate test.f it works. However, I have many...

Rename *.po to *.mo in Makefile

shell,makefile,translation,rename
I need to convert all the *.po translation files in the ./lang/ folder to *.mo files. In Makefile's "i18n" target, I have written: i18n: @for file in $(wildcard ./lang/*.po); do\ msgfmt $$file -o $(subst po,mo,$$file); \ done However, this code does not work; moreover, all the *.po files get damaged....

How to put this command in a Makefile?

awk,makefile,make,docker
I have the following command I want to execute in a Makefile but I'm not sure how. The command is docker rmi -f $(docker images | grep "<none>" | awk "{print \$3}") The command executed between $(..) should produce output which is fed to docker rmi but this is not...

Using Assembly global variable in C

c,assembly,makefile,global-variables
Trying to compile this code in a.s: section .bss global _start global TestVar TestVar: RESB 4 section .text extern main _start: and this code in b.c: extern int TestVar; void test2(int x, int y) { int z = TestVar; x = z + y; y = 1; } int main(int...

Makefile : fclean gives error if program is not yet built

makefile,make
I have 2 makefiles that crash when I use the command make re if the program (or library) is not yet previously built, because make re calls fclean, which should remove the file and crashes if the file is not found. Here is one of the makefiles for a library...

makefile read reused variable inside recipe

makefile,make
In trying to implement nonrecursive make, I have a Rules.mk which looks like: ############ # Enter Stack ############ sp := $(sp).x dirstack_$(sp) := $(d) d := $(dir) .. setup things like OBJECTS_$(d), DEPS_$(d), TARGET_$(d), etc ... ############ # Exit Stack ############ -include $(DEPS_$(d)) d := $(dirstack_$(sp)) sp := $(basename $(sp))...

Makefile refuses to match target patterns under strange circumstances

makefile,make
I encountered some strange behavior, when one runs make hello-there and the makefile is hello-%: @echo hi $* I get hi there But when the makefile is just hello-%: I get make: *** No rule to make target `hello-there'. Stop. ...

Using makefile, LD_PRELOAD to executable file

c,linux,shell,makefile
I have two files, "abc.c" and "run" and I want to make a executable binary file which perform below two intstructions gcc -m32 -O2 -Wall -DRUNTIME -shared -fPIC -o a.so abc.c -ldl LD_PRELOAD="a.so" ./run I tried to use makefile in linux, but failed. Can I use makefile to make executable...

How to install the perl module DBD::Sybase on Unix (Mac OSX)?

osx,perl,unix,makefile
I'm having trouble installing the perl module DBD::Sybase on my Mac. Please provide procedure on how to do this.

Is setting environment variable through a makefile - possible?

c,unix,makefile,malloc,gnu-make
I'd like to take advantage of MALLOC_PERTURB_ environment variables that can change memory allocation parameters (man 3 mallopt). However, I'd like to control allocation parameters on application level, not entire system level. Ideally, if I could control them through project's makefile. I've tried to change mentioned variables through makefile, yet,...

Make: How to process many input files in one invocation of a tool?

makefile,make,gnu-make
I have a data conversion process that is driven by GNU make. It takes human-generated input files and creates output files using a conversion progam. Obviously this is about as simple as a makefile can get: inputs=$(wildcard *.input) outputs=$(subst .input,.output, $(inputs)) .PHONY: all all: $(outputs) %.output: %.input converter $< -o...

ShellScript in a Makefile

bash,shell,makefile
I've written the following makefile: # make the iMe program # SDIR=src IDIR=include CFLAGS=-I$(IDIR) ODIR=obj EDIR=bin LIBS=-lrt -lpthread _DEPS = 1.h 2.h 3.h 4.h 5.h 6.h 7.h 8.h 9.h 10.h 11.h DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS)) _OBJ = 1.o 2.o 3.o 4.o 5.o 6.o 7.o 8.o 9.o 10.o 11.o OBJ =...

Undefined reference to pico_dhcp_server_initiate when compiling PicoTCP for ARM mbed

c++,c,compiler-errors,makefile,embedded
I'm working on a project where I have to work with PicoTCP (see https://developer.mbed.org/users/daniele/code/PicoTCP/, I'm using an older version of this library). In my main.cpp file, I have the following code: #include "pico_stack.h" #include "pico_dhcp_server.h" int main(void) { // create DHCP server struct pico_dhcpd_settings s = { }; s.my_ip.addr =...

What are the steps to setup an RTOS application on STM32 using Linux and Makefiles instead of using Windows based IDEs?

makefile,arm,embedded-linux,stm32,rtos
I am using STM32F4 Discovery board to develop a simple application to on-board accelerometer while simultaneously lighting respective LEDs mounted around the accelerometer device. I want to use any RTOS but I am unable to decide which one since I am new to using RTOS. If anyone could elaborate the...

Expanding directories in variables with make

r,bash,variables,path,makefile
I have a makefile (below) for a project where I've been given a folder of "Raw Data" - a set of files from a colleague, and I've made an R script that does an analysis on some of those files. What I want to do with a the makefile then...