FAQ Database Discussion Community


Make using implicit rule instead of explicit?

makefile,make,gnu-make
Here is my entire Makefile: TGT = call OBJS = main.o .PHONY : clean $(TGT) : $(OBJS) $(CC) -o [email protected] $^ %.o : %.s $(AS) -o [email protected] $< %.s : %.c $(CC) -S -o [email protected] $< clean : $(RM) $(TGT) *.o *.s When I run make, I was expecting: main.s...

Make not picking the needed target

c,makefile,make,gnu-make
I have written a make file for a program as under Panther!simpleguy:~/Code [62]$ cat make.def CC = gcc LIBS = -lpthread CODE_FILE = Code_In_C.c EXECUTABLE = Code_In_C all : ${CODE_FILE} ${CC} -o ${EXECUTABLE} ${LIBS} ${CODE_FILE} I tried to make it using below command Panther!simpleguy:~/Code [63]$ make all make.def make: ***...

Is it possible to “pass-through” GNU make jobserver environment to a submake served via a 3rd-party (non-make)

gnu-make
When running gnu-make rules with -jN make creates a jobserver for managing job-count across submakes. Additionally you can "pass the jobserver environment" to a make recipe by prefixing it with + - eg: target : +./some/complex/call/to/another/make target Now I instead of a sub-make I have a (python) script which runs...

Can Make be made to understand that a/../z and b/../z are the same location?

makefile,make,gnu-make
I have a somewhat large and complex Makefile setup that postprocesses some data files. Overall it work quite well, but I have run into an annoying issue where Make builds the same target many times over under different directory names. As a simple example, consider the Makefile foo : 1/foo...

add dependencies to a library, and add them to a binary which depends on that library

c++,makefile,gnu-make
What I have: I have a non-recursive makefile which searches for module.mk files, and includes them modules := $(shell find . -name module.mk) include $(modules) If I want to create a static library, the module.mk looks like this: $(eval $(call make-lib, test_lib)) Which will find a list of all .cpp...

Why does my GNU make skip making an object file (%.o) when building an %.s (assembler) program?

gcc,assembly,make,gnu-make
I am using implicit rules only - removing the makefile altogether for a minimal test case. I have an empty (no problem for GNU assembler) program.s file. Executing: make program Gives me following output from make: cc program.s -o program (and of course the expected errors, which here is of...

make argument passing and multiple .PHONY targets

makefile,gnu-make,argument-passing
This Makefile .PHONY contains two targets: clean and cleanx. When I entered "make clean" or "make cleanx" worked fine. But, when I do "make" in the command line, it acts like "make clean". I expected that "make" should not do anything. There must be that I misunderstood. Would you explain...

Why make doesn't echoning

makefile,make,gnu-make
I have a strange behavior with my make command. It doesn't print commands lines before executing. I know the existence of "-s", "--silent" and "--quiet" options or the usage of "@" before a command line. And I do not use any of them. For example, a very basic Makefile :...

How can I get gmake to output return codes for all commands without modifying makefile

makefile,make,return-value,gnu-make
How can I get gmake to output exit status codes for all commands without modifying the Makefile? If modifying the Makefile was an option, something like the following is possible: $(CC) -c -o [email protected] $< $(CFLAGS); echo $$? Another way that I've found so far is to wrap the command...

Gnu make: is it possible to delay include directive to secondary expansion?

include,make,gnu-make
I need to delay inclusion of dependency fragments until second expansion time because the make file I'm editing is itself an include file and I will not have a list of source files to generate the includes until secondary expansion. .SECONDEXPANSION: AUTO_DEPENDENCY_FILES = $(patsubst %.cc, depend/%.d, $(CC_SRC_FILES)) # the following...

Recursive call to makefile does not update object files

c,makefile,gnu-make
I have a makefile with a recursive call to itself. When I first run make, the object files are created and linked just fine. But when I modify a source file and run make again, the objects are not recreated (make says the target is up to date). I need...

GNU make - depend only on file existence and not modification time

linux,build,makefile,dependencies,gnu-make
I want to have a makefile in which I have a task a that can only run if a file b exists, but does not need to be re-run if b is updated. How do I do this?

GNU Make, generate file with default settings/content when absent

make,build-process,gnu-make,default-value
I would like make to either copy a file from the source tree into the target/build directory if it exits or generate an empty/default file if not. It would be easy to do the following: target/settings.json: src/settings.json cp $? [email protected] src/settings.json: echo "default..." > [email protected] But that taints the source...

Pattern rule with partial dependency

makefile,gnu-make
I have a makefile with a bunch of .R scripts that create .csv files as output. These files are then used in a python simulation. all: $(FILES) python simulation.py $(FILES): %.csv: %.R Rscript $< This is straightforward. My wrinkle is that one (and only one) of the .R scripts has...

Makefile : How to runs 2 distinct shells?

node.js,bash,makefile,gnu-make,forever
I use a makefile to store my processes. One of these processes requires a server. Also, my script.make is such : end: server script # runs the 2 other tasks, 1st `server` then `script` script: node ./node_script_with_server_queries.js server : node ./node_modules/.bin/forever ./node_modules/.bin/http-server Then I runs the makefile, is start the...

How can I make archive contents true targets of an archive extraction rule with GNU make?

makefile,gnu-make
I wish to write several rules that extract the contents of tar archives to produce a number of files that are then used as input dependencies for other rules. I wish this to work even with parallel builds. I'm not using recursive make. First up, sorry for the marathon question,...

Expanding make variables at pattern definition time

gnu-make
Here's a trivialised example of a much more complex build system that I'm working on. T := 1 $T/foo.o: $T/foo.c touch $T/foo.o # yes, I know I can use [email protected], this is an example T := 2 $T/foo.o: $T/foo.c touch $T/foo.o # yes, I know I can use [email protected], this...

Makefile - run time decisions using ifeq

makefile,gnu-make
I am trying to solve a particular problem where variables are assigned in one recipe and then interpreted in other recipes, all during run time. As I understand it, ifeq conditions are evaluated during parsing which doesn't work for me as some of them are always false. Is there a...

GNU makefile rules and dependencies

c++,linux,makefile,make,gnu-make
I've been doing a lot of reading on how to write makefiles to build an application on Linux but I'm massively confused about the many different ways to apparently achieve the same goal. This is what I have come up with so far to build an archive. SHELL = /bin/sh...

Adding debug file to makefile build?

makefile,gnu-make
I have a makefile for a project that I want to be used for debug and release builds. For the debug build I have to include an extra cpp file that holds all the unit tests. I have added a debug option to the makefile and everything seems to work...

Escaping makefile variables (for internal makefile use)

variables,make,gnu-make
Is it possible to "safely" expand a variable in a makefile, escaping all characters that makefile considers special? As an example, assume that a variable is used as a target: ${external_chaos}: dd if=/dev/zero of=${external_chaos} (drama in example intentional) If external_chaos contains spaces, ;, #, :, ,, or other makefile-significant characters,...

basic makefile ifeq how to

makefile,make,gnu-make
I am just learning about Makefiles and am having trouble with ifeq. Version = GNU Make 3.82 Here is my simple Makefile: CHECK := 0 CHECK2 := 0 check : @echo "Check=${CHECK}" @echo "Check2=${CHECK2}" ifeq (${CHECK2},${CHECK}) @echo "EQUAL" else @echo "NOT EQUAL" endif Here is the output: Check=0 Check2=0 NOT...

force a script to run at the beginning of a makefile, and display its output

makefile,gnu-make
I have a script which generates a version.h file with various details about the particular build The script runs various commands, such as: readonly VERSION=$(git describe --always --dirty --long --tags) readonly NUM_COMMITS=$(git rev-list HEAD | wc -l | bc) readonly BRANCH=$(git rev-parse --abbrev-ref HEAD) readonly AHEAD_BY=$(git log --oneline origin/${BRANCH}..${BRANCH} |...

Simple Makefile reporting circular dependency — possibly from suffix rules?

makefile,make,gnu-make,circular-dependency
I'm using mingw32-make and attempting to create a simple rule to run windres to include an icon for a Windows executable. The structure consists of a simple C program in a.c, an a.rs file containing only the line: 1 ICON "a.ico" ..the icon file itself, and the Makefile. The Makefile:...

Open Pegasus 2.14.1 client connection issue

c++,openssl,gnu-make,wbem
I would like to build new version of Open Pegasus Client (2.14.1). Unfortunately I'm facing with some build issues. Does anybody know some workaround for these issues? My environment is: OS: Windows 8.1 Enterprise Make version: GNU Make 3.81 Pegasus sources version: 2.14.1 OpenSSL version: 1.0.2a My scenario is quite...

Examples for “How make file is read”

makefile,make,gnu-make
In the GNU-Make manual the How make Reads a Makefile https://www.gnu.org/software/make/manual/make.html#Reading-Makefiles sections says GNU make does its work in two distinct phases. During the first phase it reads all the makefiles, included makefiles, etc. and internalizes all the variables and their values, implicit and explicit rules, and constructs a dependency...

Number of parallel build jobs in recursive make call

makefile,make,gnu-make
I have a makefile which wraps the real build in a single recursive call, in order to grab and release a license around the build, regardless of whether the build succeeds. Example: .PHONY main_target main_target: @license_grab & @sleep 2 [email protected]$(MAKE) real_target @license_release This works great, until I want to run...

GMake Echo Not Working Correctly, Dropping Backslash ( \ )

windows,gnu-make
I'm having issues getting GMake to work. It was fine as of late last week. I reinstalled my compiler to a new location on this machine and ran a quick (successful) build, but haven't built anything since. Currently, output from GMake looks as follows IDE LSL Lib MCAL_CA MCAL_DB Output...

Visual Studio Make instead of GNU Make with Cygwin

make,cygwin,gnu-make
I'm still trying to build VTK on windows. I have installed Cygwin and I'm done configuring with CMake I think. However I'm facing the error that you can see on the screenshot below: the make command somehow tries to make through MS Visual Studio while I want to use the...

Match-Anything Pattern Rules

make,gnu-make
I am using GNU Make 3.81 version. From the following example, I expect match anything pattern(%:) has to be print. Instead of that te%: has executed. Can some one explain, why target '%:' did not run? Is this not match all file name? Makefile: all: test echo [email protected] %: echo...

Setting the variables in Makefile target not working as expected

variables,makefile,gnu-make
I have a simple Makefile where I would like to set a variable in one of the targets (so that I can use this variable in other targets). My simple Makefile: VAR=DEFAULT import: echo [email protected] [email protected] echo $(VAR) Output when I run "make import": echo import import VAR=import echo DEFAULT...

Apply distinct flags when compiling a subset of the sources

makefile,make,gnu-make
I have two sets of source files in my project from which I need to generate object files. SET_ONE = foo.o bar.o SET_TWO = zerz.o zork.o I want to pass add an extra option to CFLAGS when building the files in SET_ONE but not for those in SET_TWO. For example,...

GNU Make, building unnecessary dependencies

make,gnu-make
In my makefile I have a rule alike this; res/resource.me: res/lengthy_dependency ... code that builds resources.me assuming lengthy_dependency is present ... res/lengthy_dependency: ... Download 10GB data and stuff ... This is all nice and dandy, however when running res/resource.me while it is built and res/lengthy_dependency is removed to save space....

How can I use a pattern rule to add prerequisites like I can to define variables?

makefile,make,gnu-make
I have the following Makefile: all: foo/bar/baz foo/%: @echo $(VAR) cp [email protected] [email protected] # This works foo/bar/%: VAR := Hello world # This doesn't foo/bar/%: foo/bar/%.in foo/bar/baz.in: touch [email protected] When I run it, the output is Hello world cp foo/bar/baz.in foo/bar/baz cp: cannot stat ‘foo/bar/baz.in’: No such file or directory...

makefile library dependencies - resolve circular dependency

c++,makefile,gnu-make
I am trying to build a feature into my makefile which allows me to specify a list of libraries a particular library depends on This will allow dependants of a library to automatically be rebuilt if that library's dependencies are rebuilt, and also have the dependencies added to the link...

Delegating targets to other make files, in parallel, without include

makefile,make,gnu-make
Say I have a Makefile: foo: T = a b c bar: T = d e f foo bar: $(MAKE) -f Makefile.other $(T) This does the wrong thing on make -j foo bar if Makefile.other encodes dependency information between a b c and d e f. Is there a way...

No rule to make target

c,makefile,gnu-make
I am trying to follow this tutorial: http://www.cs.colby.edu/maxwell/courses/tutorials/maketutor/ When I am at the last makefile (#5), the "make" can't proceed becasue (error prompt) No rule to make target "obj/hellomake.o", needed by "hellomake". This piece of code tries to compile the sources files and put libs, srcs, objs into respective folders....

% not matching zero or more characters in rule?

makefile,gnu-make
According to the manual on Defining and Redefining Pattern Rules (and if I am reading it correctly): ‘%’ character matching any sequence of zero or more characters... But the following is not matching both bench.cpp and bench2.cpp: bench%.o : bench%.cpp $(CXX) $(CXXFLAGS) -DCRYPTOPP_DATA_DIR='"$(PREFIX)/share/cryptopp"' -c $< %.o : %.cpp $(CXX) $(CXXFLAGS)...

Dot in front of variables in make files

makefile,make,gnu-make
I am not able to figure out what does a dot . in front of a variable in makefile does. For e.g.: SOURCEDIRS = . $(PROJECTDIRS) $(TARGET_DIRS_CONCAT) vpath %.c $(SOURCEDIRS) It would be great if someone could tell me. Thanks!...

Make: How to process many input files in one invocation of a tool?

makefile,make,gnu-make
I have a data conversion process that is driven by GNU make. It takes human-generated input files and creates output files using a conversion progam. Obviously this is about as simple as a makefile can get: inputs=$(wildcard *.input) outputs=$(subst .input,.output, $(inputs)) .PHONY: all all: $(outputs) %.output: %.input converter $< -o...

make: Nothing to be done for `all'. on Target That Just Calls Another Makefile

makefile,gnu-make
Say I have the following gnu makefile. TOP := $(dir $(lastword $(MAKEFILE_LIST))) all : graphics graphics : pushd $(TOP)../graphics; \ $(TOP)../tools/autotools_gen.sh; \ ./configure; \ $(MAKE) clean all; \ $(TOP)../tools/autotools_clr.sh; \ popd; inside a folder called build and I call it from one directory up, in the following manner: make --file...

What does the following makefile command do? /no-symbols-control-file

makefile,make,gnu-make,binaryfiles,contiki
I cam across the following command in a makefile: %-nosyms.$(TARGET).elf: %.co $(PROJECT_OBJECTFILES) $(INTERRUPT_OBJECTFILES) contiki-$(TARGET).a $(CC) $(CFLAGS) -o [email protected] $(filter-out %.a,$^) $(filter %.a,$^) $(filter %.a,$^) $(LDFLAGS) Source: Contiki/cpu/arm/stm32f103/Makefile.stm32f103 . Does this command generate no-symbols-control-file? What is the use of a no symbol image file?...

How to get Cartesian product (combinatorial expansion) of name lists in makefile

makefile,gnu-make,cartesian-product
Using GNU-make, say that I have two lists in my Makefile, and I want to combine them to get their Cartesian product as another list, so that I can use it as a list of targets. As an example from a different language that I know better, R has a...

Why Bash-in-Makefile expression doesn't work?

bash,makefile,gnu-make
Directly pasted into my shell, the following tries each of the 3 regex and works (see the *.{jpg,png,gis.tif}): for file in ./output/India/*.{jpg,png,gis.tif}; do echo $file; openssl base64 -in $file -out ./output/India/`basename $file`.b64; done; As a makefile process, it fails and returns : task: for file in ./output/India/*.{png,jpg,gis.tif} ; \ do...

Autodependency generation in makefiles

makefile,make,gnu-make,makefile-project,multiple-makefiles
I am trying to understand how autodependency is generated in makefiles in the given link, i cannot understand the following piece of code: DEPDIR = .deps df = $(DEPDIR)/$(*F) SRCS = foo.c bar.c ... %.o : %.c @$(MAKEDEPEND); \ cp $(df).d $(df).P; \ sed -e 's/#.*//' -e 's/^[^:]*: *//' -e...

GNU make equivalent to BSD make's $(var:Q)?

makefile,make,gnu-make,bsdmake
BSD make has a :Q variable expansion modifier, documented in the FreeBSD make man page as follows: :Q Quotes every shell meta-character in the variable, so that it can be passed safely through recursive invocations of make. If variable var has value a b\c"d'e$f, then $(var:Q) expands to a\ b\\c\"d\'e\$f...

Filtering using multiple wildcards

make,filtering,wildcard,gnu-make,glob
I've git a project where, at some point in its Makefile, I'm filtering out stuff from a certain directory: relevant = $(filter-out irrelevant/%,$^) Now I want to use this in a VPATH-enabled environment. So the paths of my dependencies in $^ might not start with irrelevant any more, but instead...

Automatic dependency processing in Makefile

makefile,make,gnu-make
I have a simple makefile. IDIR =./include CC=gcc CFLAGS=-I$(IDIR) SRCDIR = ./src ODIR=obj LDIR =./lib LIBS=-lm SRC = hellomake hellofunc OBJ = ${SRC:%=$(ODIR)/%.o} _DEPS = hellomake.h DEPS = ${_DEPS:%=$(IDIR)/%} $(ODIR)/%.o: $(SRCDIR)/%.c $(DEPS) $(CC) -c -o [email protected] $< $(CFLAGS) hellomake: $(OBJ) gcc -o [email protected] $^ $(CFLAGS) $(LIBS) .PHONY: clean clean: rm...

Cannot write redirection symbol(>>) to text file using nmake

makefile,make,gnu-make,nmake
I have a make file which outputs some data to a text file. Commands shown below: @echo HOURS >> 123.txt @echo MINUTES >> 123.txt @echo SECONDS >> 123.txt As of now the 123.txt file contains HOURS MINUTES SECONDS I would like to append a text such as >> to the...

`make depends` magic in gnu make?

makefile,make,gnu-make
I have a simple script (depends.sh) that generates the dependency file, and made some changes from the dependency file. #!/bin/sh #echo "## Got: $*" CC="$1" DIR="$2" shift 2 case "$DIR" in "" | ".") $CC -MM -MG "[email protected]" | sed -e '[email protected]^\(.*\)\.o:@\1.d \1.o:@' ;; *) $CC -MM -MG "[email protected]" |...

main() used as a function and CLI

c++,build,g++,gnu-make,entry-point
I have several source files that run together as anonymous publish/subscribe nodes. There is a main function that collects all the nodes and launches them through their start functions. // main.cpp #include "nodeA.h" #include "nodeB.h" int main(int argc, char *argv[]) { /* some argument parsing here */ start_node_a(argc, argv); start_node_b(argc,...

trying to install valgrind but stuck at make valgrind, how?

c,make,valgrind,gnu-make
This might be a silly question, actually I have just started with it. I am following a tutorial to LCTHW and I am trying to install valgrind, the author specifies steps: 1) Download it (use wget if you don't have curl) curl -O http://valgrind.org/downloads/valgrind-3.6.1.tar.bz2 use md5sum to make sure it...

GNU make is adding an extra step not in my Makefile that causes all sorts of linker errors. What's going on?

makefile,gnu-make
Given the following makefile for GNU make: # TODOs so I don't forget: # - make debugging an option # - make 64 below an actual option # - figure out why make test seems to rebuild the DLL # - __declspec(dllimport) ifeq ($(MAKECMDGOALS),64) CC = x86_64-w64-mingw32-gcc RC = x86_64-w64-mingw32-windres...

Can iarbuild run in parallel mode?

gnu-make,iar
I am using iarbuild in command line to build my projects on a 8-core PC. The build speed is quite slow and it smells the multicore PC's is not fully utilized. Is there a build option that can make the build running in parallel mode? (Like in GNU make, there...

What kind of syntax is this in Makefile? (A := $(B.$(C).D))

android,makefile,make,gnu-make
TARGET_DEVICE := $(PRODUCTS.$(INTERNAL_PRODUCT).PRODUCT_DEVICE) It comes from the Android makefile. The using of dot(.) is confusing me, What kind of syntax is this? Any keyword related to this syntax?...

How to programmatically define targets in GNU Make?

makefile,gnu-make,bsdmake
I am not aware of any way to define programatically targets in GNU Make. How is this possible? Sometimes one can go away with alternate methods. The ability to define programatically targets in Makefiles is however a very important to write and organise complex production rules with make. Examples of...

Compile nodejs 10.36 for armv7 on armv7

node.js,gcc,embedded-linux,gnu-make,armv7
I try to compile to compile node.js on an embedded linux in a chroot (armel wheezy) environment. The system has all necessary versions of tools. Python 2.7.3 GCC 4.6 GNU Make 3.81 CPUInfo: Processor : ARMv7 Processor rev 10 (v7l) processor : 0 BogoMIPS : 790.52 processor : 1 BogoMIPS...

Is setting environment variable through a makefile - possible?

c,unix,makefile,malloc,gnu-make
I'd like to take advantage of MALLOC_PERTURB_ environment variables that can change memory allocation parameters (man 3 mallopt). However, I'd like to control allocation parameters on application level, not entire system level. Ideally, if I could control them through project's makefile. I've tried to change mentioned variables through makefile, yet,...

Which operating systems support passing -j options to sub-makes?

make,gnu-make
From the man page for gnu make: The ‘-j’ option is a special case (see Parallel Execution). If you set it to some numeric value ‘N’ and your operating system supports it (most any UNIX system will; others typically won’t), the parent make and all the sub-makes will communicate to...