c,makefile , Makefile: wildcard and patsubst does not change file source names


Makefile: wildcard and patsubst does not change file source names

Question:

Tag: c,makefile

I am trying to write a Makefile for my project, all the *.c and *.h files are in a folder called src, and the Makefile looks like this --

CC              := gcc
CFLAGS          := -g -Wall -ansi -pedantic -std=gnu99
LDFLAGS         := -lm 
INCLUDES        := $(wildcard src/*.h)
IFLAGS          := $(addprefix -I/,$(INCLUDES))
SRC             := $(wildcard src/*.c)
OBJS            := $(patsubst %.c, %.o, $(SRC))
APP             := app

all: $(OBJS)

$(APP): $(OBJS)
    $(CC) $(CFLAGS) $< -o [email protected] $(LDFLAGS)

$(OBJS): $(SRC) $(INCLUDES)
    $(CC) $(CFLAGS) $(IFLAGS) -c $< -o [email protected]

clean:
    rm -rf $(OBJS)
    rm -rf *.out
    rm -f $(APP)

At this point I am not building the executable, just trying to compile them to object files, so when I run, I am getting this output --

gcc -g -Wall -ansi -pedantic -std=gnu99 -I/src/structure.h -I/src/rng.h -c src/allocate.c -o src/allocate.o
gcc -g -Wall -ansi -pedantic -std=gnu99 -I/src/structure.h -I/src/rng.h -c src/allocate.c -o src/auxiliary.o
gcc -g -Wall -ansi -pedantic -std=gnu99 -I/src/structure.h -I/src/rng.h -c src/allocate.c -o src/decode.o
gcc -g -Wall -ansi -pedantic -std=gnu99 -I/src/structure.h -I/src/rng.h -c src/allocate.c -o src/display.o

You can see that in each gcc invocation, the source file names do not change, they are all always src/allocate.c why ? However, the object names are correctly expanded like src/allocate.o, src/auxiliary.o and src/decode.oetc.


Answer:

It seems you've mixed up some things here.

They are basically two type of rules you need to use here, and they both share the same syntax:

targets : prerequisites
    recipe

When you write this:

$(APP): $(OBJS)
    $(CC) $(CFLAGS) $< -o [email protected] $(LDFLAGS)

You're saying to make that you want to create $(APP), and to do that you need $(OBJS) to exist or to be created.

Now when you write this:

$(OBJS): $(SRC) $(INCLUDES)
    $(CC) $(CFLAGS) $(IFLAGS) -c $< -o [email protected]

You're telling make you want to create a list of .o files, and for each individual file that you need all $(SRC) and $(INCLUDES).

Since in the recipe you're using $<, which is a shortcut for the first entry in the prerequisites list, you always end up with the same source file being compiled.


To do what you want, you must abstract things a little bit and tell make "Here is how I want you to build any .o file that depends on a corresponding .c". That is the job of pattern rules:

%.o: %.c
    $(CC) $(CPPFLAGS) $(CFLAGS) -o [email protected] -c $<

Ultimately, your Makefile should look like this:

APP             := app
SRC             := $(wildcard src/*.c)
OBJ             := $(SRC:.c=.o)
CFLAGS          := -W -Wall -g -std=c99 -pedantic
LDLIBS          := -lm

all: $(OBJS)

$(APP): $(OBJ)
    $(CC) $(LDFLAGS) $^ $(LDLIBS) -o [email protected]

clean:
    $(RM) $(APP) $(OBJ)

Note another couple of things here that you missed:


To address the comments:

GNU make has a lot of predefined rules, functions and variables that you should be using before rolling your own. It has basic rules for compiling and linking C and C++ programs, among other, this is why your Makefile does not need te redefine the %.o: %c rule that already exists.

You can see all of these by typing this in your favorite shell:

$ make -p > predefined.mk

$(RM), $(CC) are one of these predefined variables, you can see by yourself what they actually contain.

Now, as many users are concerned with header files dependencies, let's adress this issue. You won't have to manually do that, modern compilers like GCC and Clang do this for you once you set them up.

The dependencies for each .c file will be generated in a .d file that must be included in the Makefile.

To tell the compiler to generate these files while compiling, you need to pass a preprocessor flag:

CPPFLAGS := -MMD

Now the dependencies are auto-generated, we need to include them:

DEP := $(OBJ:.o=.d)

-include $(DEP)

You'd also want to clean them:

clean:
    $(RM) $(APP) $(OBJ) $(DEP)

Now your Makefile looks like this:

APP             := app
SRC             := $(wildcard src/*.c)
OBJ             := $(SRC:.c=.o)
DEP             := $(OBJ:.o=.d)
CPPFLAGS        := -MMD
CFLAGS          := -W -Wall -g -std=c99 -pedantic
LDLIBS          := -lm

all: $(OBJS)

$(APP): $(OBJ)
    $(CC) $(LDFLAGS) $^ $(LDLIBS) -o [email protected]

clean:
    $(RM) $(APP) $(OBJ) $(DEP)

-include $(DEP)

Last point: the syntax $(SRC:.c=.o) is a shortcut for $(SRC:%.c=%.o) which is also a shortcut for $(patsubst %.c,%.o,$(SRC)).


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