makefile,autotools,autoconf , How to deal with autoconf warning “'%'-style pattern rules are a GNU make extension”
How to deal with autoconf warning “'%'-style pattern rules are a GNU make extension”
Question:
Tag: makefile,autotools,autoconf
In a Makefile with
%.o: %.c
@echo Compiling $< ...
I'm getting the warning '%'-style pattern rules are a GNU make extension when I run autoreconf --install (of autoconf version 2.69). The warning is not very clear, but makes me think that there's something to be added to configure.ac.
I conducted searches on google.com, duckduckgo.com and yahoo.com, but they all don't seem to be able to differentiate between the large number of build logs they index (why should they...) which makes the search painful. I figured that:
- I can silence the warning by adding
AM_INIT_AUTOMAKE([-Wno-portability]) to configure.ac (found in a post of the openais mailing list) which seems not great because simply silencing a warning is generally not a good idea in a technical environment - please tell me if GNU autotools is an exception.
Answer:
Replace
%.o: %.c
with
.c.o:
That's a suffix rule doing the same thing, and it's more portable. If your rule involves a suffix that is not known to make, list it in the prerequisites for the special .SUFFIXES target:
.SUFFIXES: .hack .win
.hack.win:
# build a .win file from a .hack file.
More on how this works in detail here. They recommend to use pattern rules instead of suffix rules because they're clearer and more general, which is true, but as autoconf notes, they are indeed less portable. So if that is a worry (if you want to build on BSD/Mac OS and not install GNU make, basically), fall back on the "old-fashioned suffix rules."
If you have a pattern rule that cannot be replaced by a suffix rule, another possible replacement that automake doesn't complain about is a static pattern rule. This is similar to a pattern rule but requires a list of targets it applies to. Instead of saying
%.o: %.c
You would have to say
OBJS = foo.o bar.o baz.o # list all .o files here
$(OBJS): %.o: %.c
Or more generally,
target-pattern: prerequisite-pattern
is replaced by
target-list: target-pattern: prerequisite-pattern
Related:
makefile,make
There are some C code: apple.c #include<stdio.h> int main(void) { printf("apple\n"); return 0; } Makefile apple: gcc -c [email protected] gcc [email protected] -o [email protected] $ make apple and it works perfectly. But if I modify Makefile as: apple: gcc -c $1.c gcc $1.o -o $1 $ make apple It does not...
c,makefile
This is my situation, I am trying to write a Makefile for my c program, it has these components -- 2 Headers: src/header1.h src/header2.h N Sources: src/src1.c src/src2.c src/src3.c ... src/srcn.c 2 Mains: src/main1.c src/main2.c main1.c and main2.c takes all the same src*.c and header*.h files, but in a different...
c++,c,makefile,make
Why this rule cannot override the default implicit rule ? When make is invoked like: make myapp (suppose myapp.c is there). The make runs the default command to build and link the program instead the commands defined in this implicit rule: #... omitted code LCUS=$(LIBS)/libcus.a #... omitted code % :...
github,go,makefile,travis-ci
Essentially what I want to do is embed the git tag name (from a github release) to a version string within my GO code. If I use this code; package main import ( "flag" "fmt" ) var version string func main() { var verFlag bool flag.BoolVar(&verFlag, "version", false, "Returns the...
c++,makefile,cmake
I would like to ask how to convert Makefile to CMAKEList. Currently I can compile CMAKEList. However, the program doesn’t behave like the program generated out of Makefile program. details: 1. This is my Makefile #=========================================================================== # Makefile for behavior_program #--------------------------------------------------------------------------- # [Update log] #=========================================================================== TARGET = PFforAEV0.2.2 CC =...
c,assembly,makefile,global-variables
Trying to compile this code in a.s: section .bss global _start global TestVar TestVar: RESB 4 section .text extern main _start: and this code in b.c: extern int TestVar; void test2(int x, int y) { int z = TestVar; x = z + y; y = 1; } int main(int...
eclipse,makefile,make
I have a project with a Makefile in it, on Unix console it works fine, compiles, builds and I can run the binary at the end. I imported the project into Eclipse workspace and somehow Makefile module of Eclipse cannot build the project now. It gives the following error: g++:...
makefile,make
In trying to implement nonrecursive make, I have a Rules.mk which looks like: ############ # Enter Stack ############ sp := $(sp).x dirstack_$(sp) := $(d) d := $(dir) .. setup things like OBJECTS_$(d), DEPS_$(d), TARGET_$(d), etc ... ############ # Exit Stack ############ -include $(DEPS_$(d)) d := $(dirstack_$(sp)) sp := $(basename $(sp))...
osx,makefile,frameworks,fortran
This question already has an answer here: How to use LDFLAGS in makefile 2 answers I wish to compile Fortran source code which uses functions from LAPACK and BLAS. When I compile a single source code file e.g. gfortran -g -framework accelerate test.f it works. However, I have many...
c++,c,makefile
What is the difference between .cpp.o:, .o: and %.o: %.c? Here's a simple Makefile example: CC=g++ CFLAGS=-c -Wall SOURCES=file1.cpp file2.cpp OBJECTS=$(SOURCES:.cpp=.o) EXECUTABLE=dbase $(EXECUTABLE): $(OBJECTS) $(CC) $(OBJECTS) -o [email protected] #.o: #.cpp.o: %.o: %.c $(CC) $(CFLAGS) $< -o [email protected] all: $(SOURCES) $(EXECUTABLE) clean: rm -rf $(OBJECTS) $(EXECUTABLE) I noticed that the output...
c++,makefile,make
I am working with cygwin on windows 8.1. I have used the following make file .SUFFIXES : .o .C CFLAGS = -g2 CC =g++ ${CFLAGS} LIBRARIES = -lm .C.o : ${CC} -c $< SOURCE-FILES = sparsegraph.C myvarious.C pairlist.C graphlist.C peo.graph.C choldc.C copy.C metropolis_fns.C likelihood.C metropolis.C OBJECT-FILES = sparsegraph.o myvarious.o pairlist.o...
makefile,make,gnu-make,binaryfiles,contiki
I cam across the following command in a makefile: %-nosyms.$(TARGET).elf: %.co $(PROJECT_OBJECTFILES) $(INTERRUPT_OBJECTFILES) contiki-$(TARGET).a $(CC) $(CFLAGS) -o [email protected] $(filter-out %.a,$^) $(filter %.a,$^) $(filter %.a,$^) $(LDFLAGS) Source: Contiki/cpu/arm/stm32f103/Makefile.stm32f103 . Does this command generate no-symbols-control-file? What is the use of a no symbol image file?...
c,unix,makefile,malloc,gnu-make
I'd like to take advantage of MALLOC_PERTURB_ environment variables that can change memory allocation parameters (man 3 mallopt). However, I'd like to control allocation parameters on application level, not entire system level. Ideally, if I could control them through project's makefile. I've tried to change mentioned variables through makefile, yet,...
makefile
I have a short Make script, which works if I put the Build directory in as a string manually myself instead of as a variable: CC = gcc CFLAGS = -O2 -g -Wall -fmessage-length=0 LDFLAGS = SRCDIR = Src BUILDDIR = Build SRCS = $(SRCDIR)/Main.c OBJS = $(SRCS:.c=.o) LIBS =...
makefile,make
Typically we have this in a Makefile %.o:%.c $(cc) $(flags) -o [email protected] -c $< When the amount of flags is huge, I feel better to write this instead %.o:%.c $(info $(cc): $< --> [email protected]) @$(cc) $(flags) -o [email protected] -c $< However it can be useful to sometime see everything. So...
shell,makefile,make
I am trying to loop through the .c files in a specific directory through the makefile. i used the following code, but it seems not working: DIR= Sources \ Sources_2 @for entry in ${DIR} ; \ do \ @for i in $${entry}/*.c ; \ do \ echo "Processing $${i}"; \...
assembly,makefile,nasm
I'm having trouble building a makefile for a library in nasm, since it requires that you run nasm with one input file at a time. I have tried with the %.o : %.s thing but I'm probably doing it incorrectly since it's not working. Here is what I have: NAME...
linux,build,makefile,dependencies,gnu-make
I want to have a makefile in which I have a task a that can only run if a file b exists, but does not need to be re-run if b is updated. How do I do this?
gcc,clang,autotools,compiler-options
We use autotools as our build infrastructure, and we use clang and gcc as compilers. Recently we hit a gcc warning that needed --param max-vartrack-size=100000000 to silence (without completey disabling gcc's vartracking). Clang doesn't accept that option and produces argument unused during compilation: '--param max-vartrack-size=100000000' To silence that, clang needs...
c++,qt,makefile,qt5,qmake
I have a QT project that installs a service to the system, when running make install. The relevant parts of the .pro file are the following: init.path = /etc/init.d/ init.files = myservicename updaterc.path = /etc/init.d/ updaterc.extra = chmod 755 $$init.files; \ update-rc.d $$init.files defaults 97 03; \ service $$init.files start...
c++,linux,makefile,linker,intel-mkl
I am trying to learn how a Makefile should look like, when it comes to the flags, especially the linking ones. Here is my Makefile: OBJS = n.o SOURCE = n.cpp # HEADER = there are no header files, so I commented that OUT = test CXX = ../mpich-install/bin/mpic++ FLAGS...
c,makefile,autotools,automake
New to using autoconf and automake, I am following this to learn them. I have a question regarding Makefile.am file. For a simple helloworld program below Makefile.am works: AUTOMAKE_OPTIONS = foreign bin_PROGRAMS = helloworld helloworld_SOURCES = hello.c How do we specify multiple source files (if there are multiple source files...
makefile,cmake,mingw,cmake-gui
I have a "CMakified" version of CryptoPP and I am using CMake-GUI to create a MakeFile which ming-make could process as shown in the image below. The "MakeFile" creation was successful but when I executed mingw32-make.exe I got below errors at the very end. Linking CXX executable cryptest.exe CMakeFiles\cryptest.dir/objects.a(test.cpp.obj):test.cpp:(.text+0x8e82): undefined...
makefile,gnu-make
I have a makefile with a bunch of .R scripts that create .csv files as output. These files are then used in a python simulation. all: $(FILES) python simulation.py $(FILES): %.csv: %.R Rscript $< This is straightforward. My wrinkle is that one (and only one) of the .R scripts has...
c++,makefile,export
I want to export something directly in my Makefile so I did a rule like this one : export: export LD_LIBRARY_PATH=./smthing/here And then I call this rule in my $(NAME) $(NAME): $(OBJS) $(CXX) -o $(NAME) $(OBJS) $(CXXFLAGS) $(LDFLAGS) $(export) $(OBJS) is a simple rule to convert all my .cpp into...
makefile,make,gnu-make
I have a somewhat large and complex Makefile setup that postprocesses some data files. Overall it work quite well, but I have run into an annoying issue where Make builds the same target many times over under different directory names. As a simple example, consider the Makefile foo : 1/foo...
makefile
Based on this paper, I'm trying to rework a subset of my build system to be non-recursive. It's actually working pretty well. By default, I have part of my makefile include all the relevant directories via a template: DIRECTORIES = dirA dirB ... etc ... define import_template dir := $(1)...
c++,c,gcc,makefile
I work with C and C++ and thanks to this answer I was able to compile and run my project. Now I am writing a makefile to spare time. But things are getting complicated : Project structure project makefile client bin src c cc java server ... # Directories #...
c++,xcode,makefile,make
I'm trying to compile an existing c++ project, originally developed on linux with gcc. The only external library is GSL (GNU Scientific Library). I have created an external build tool project to use xcode's debugger, but I currently have two issues. 1) When I try to build in xcode it...
c++,c,struct,makefile
I am having trouble understanding an answer I saw in another post. It said that it is good practice to define a struct in a separate .h file so it can be used in other files. I think that is great and it solves my current dilemma, however I have...
c,makefile
I'm trying to write a Makefile that when I add some deps in my application I just have to change DEPS_NAME variable, but something is wrong and I can't figure out what. I know that this is not the only problem with this Makefile, I just started to study this...
c,makefile
I am trying to write a Makefile for my project, all the *.c and *.h files are in a folder called src, and the Makefile looks like this -- CC := gcc CFLAGS := -g -Wall -ansi -pedantic -std=gnu99 LDFLAGS := -lm INCLUDES := $(wildcard src/*.h) IFLAGS := $(addprefix -I/,$(INCLUDES))...
makefile,make,gnu-make
I am not able to figure out what does a dot . in front of a variable in makefile does. For e.g.: SOURCEDIRS = . $(PROJECTDIRS) $(TARGET_DIRS_CONCAT) vpath %.c $(SOURCEDIRS) It would be great if someone could tell me. Thanks!...
gcc,makefile,g++
I am using gcc 4.8.2, and I am trying to build both the object file and the dependency file concurrently. This works: $ g++ -std=c++11 -MP -MD -c foo.cxx -o foo.o $ [ -s foo.d ] && [ -s foo.o ] && echo yay yay However, instead of generating foo.d,...
makefile,arm,embedded-linux,stm32,rtos
I am using STM32F4 Discovery board to develop a simple application to on-board accelerometer while simultaneously lighting respective LEDs mounted around the accelerometer device. I want to use any RTOS but I am unable to decide which one since I am new to using RTOS. If anyone could elaborate the...
c++,makefile
I have 2 .cpp files : main.cpp A.cpp and few header files in include dir. I am trying to write a makefile that recompiles whenever a header file changes. Now I tried following the method outlines in the example here. However I could not get started. Here is my attempt...
linux,makefile,cmake,make
I use UBuntu 14.04 LTS. I need to build webkitgtk 2.8.3 Here is an example instruction which I have used: linuxfromscratch When I run sudo make -j8 I get following log: Scanning dependencies of target JavaScriptCore-4-gir Scanning dependencies of target fake-generated-webkitdom-headers [ 0%] Scanning dependencies of target WebKit2-fake-api-headers Scanning dependencies...
makefile,make,gnu-make
I am just learning about Makefiles and am having trouble with ifeq. Version = GNU Make 3.82 Here is my simple Makefile: CHECK := 0 CHECK2 := 0 check : @echo "Check=${CHECK}" @echo "Check2=${CHECK2}" ifeq (${CHECK2},${CHECK}) @echo "EQUAL" else @echo "NOT EQUAL" endif Here is the output: Check=0 Check2=0 NOT...
c++,osx,twitter,makefile,clang
I am attempting to install twitcurl on OS X and have met with some problems. At first, running make would return the clang error: ld: unknown option: -soname. I looked through the responses from other users with similar problems on OS X and found the following advice: In the makefile,...
makefile,fortran,fortran90
I have a fortran main program called solidsolver.f90, and a module called read_mesh.f90. The module contains two subroutines and is used in the main program. I can compile them manually but not with a makefile. My makefile is named makefile.makefile, and it gives me an error: make: *** No targets...
c++,makefile,gnu-make
What I have: I have a non-recursive makefile which searches for module.mk files, and includes them modules := $(shell find . -name module.mk) include $(modules) If I want to create a static library, the module.mk looks like this: $(eval $(call make-lib, test_lib)) Which will find a list of all .cpp...
autotools,autoconf,automake,m4
Ok, so I am trying to make a project with Autotools, and I am trying to generate parts of my .conf file. The program needs to read from $(pkgdatadir), but I know that it is initialized in Makefile.in, so I instead substitued datadir and PACKAGE. configure.ac: AC_PREREQ([2.69]) AC_INIT([foo], [1.0.0], [[email protected]])...
c++,makefile,gnu-make
I am trying to build a feature into my makefile which allows me to specify a list of libraries a particular library depends on This will allow dependants of a library to automatically be rebuilt if that library's dependencies are rebuilt, and also have the dependencies added to the link...
bash,makefile
I'm trying to prompt user input but I'm having trouble to get read -p prompt getting printed as expected when run from within a Makefile or a subshell started by a Makefile. Here are my attempts on achieving this without success: test1: @echo '>> before input <<'; \ read -p...
c++,build,makefile
I wrote some c++ files and after compiling with out make file it works fine . But when using make file it pop out some errors . My codes are : include directory files : application.h #ifndef APPLICATION_H #define APPLICATION_H #include "employee.h" #include "employee_data.h" #include "employee.h" ...some defintions here... #endif...
makefile,make,gnu-make,makefile-project,multiple-makefiles
I am trying to understand how autodependency is generated in makefiles in the given link, i cannot understand the following piece of code: DEPDIR = .deps df = $(DEPDIR)/$(*F) SRCS = foo.c bar.c ... %.o : %.c @$(MAKEDEPEND); \ cp $(df).d $(df).P; \ sed -e 's/#.*//' -e 's/^[^:]*: *//' -e...
linux,makefile
I am trying to learn how to read makefiles and came across this one. My question is referring to the rule with target %.c. On the first command. where it says %.c: %.psvn psvn2c_core.c psvn2c_state_map.c psvn2c_abstraction.c ../psvn2c $(PSVNOPT) --name=$(*F) < $< > [email protected] What does $(*F) < $ < >...
c,makefile
I'm trying to make a makefile for a simple calculator for a college project. I need it done, and I've searched the web for tutorials and I eventually found this code: IDIR =include CC=gcc CFLAGS=-I$(IDIR) ODIR=obj LDIR=lib SDIR=src LIBS=-lm _DEPS = calc.h DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS)) _OBJ = calc.o libcalc.o...
c++,gcc,makefile,g++
I have a simple project - it has a foo.cxx and a bar.h: // bar.h // nothing // foo.cxx #include "bar.h" // nothing else If I include bar.h with ""s, then the dependency file has everything with its full paths: $ g++ -std=c++11 -MP -MMD -MF /home/barry/sandbox/foo.d -c /home/barry/sandbox/foo.cxx -o...